IRS20955(S)PbF
www.irf.com 4
Electrical Characteristics
V
CC
,V
BS
= 12 V, I
DD
=5 mA, V
SS
=20 V, V
S
=0 V,C
L
=1 nF and T
A
=25 °C unless otherwise specified.
Symbol Definition Min Typ Max Units Test Conditions
Low-Side Supply
UV
CC+
V
CC
supply UVLO positive threshold 8.4 8.9 9.4
UV
CC-
V
CC
supply UVLO negative threshold 8.2 8.7 9.2
V
I
QCC
Low-side quiescent current - - 3 mA V
DT
= V
CC
V
CLAMPL
Low-side Zener diode clamp voltage 19.6 20.4 21.6 V I
CC
=5 mA
High-Side Floating Supply
UV
BS+
High-side well UVLO positive
threshold
8.0 8.5 9.0
UV
BS-
High-side well UVLO negative
threshold
7.8 8.3 8.8
V
I
QBS
High-side quiescent current - - 1 mA
I
LKH
High-side to low-side leakage current - - 50 µA V
B
=V
S
=200 V
V
CLAMPH
High-side Zener diode clamp voltage 19.6 20.4 21.6 V I
BS
=5 mA
Floating Input Supply
UV
DD+
V
DD
, V
SS
floating supply UVLO
positive threshold
8.2 8.7 9.2 V
SS
=0 V
UV
DD-
V
DD
, V
SS
floating supply UVLO
negative threshold
7.7 8.2 8.7
V
V
SS
=0 V
I
QDD
Floating input quiescent current - - 1 mA V
DD
=9.5 V +V
SS
V
CLAMPM
Floating input Zener diode clamp
voltage
9.8 10.2 10.8 V I
DD
=5 mA
I
LKM
Floating input side to low-side leakage
current
- - 50 µA V
DD
=V
SS
=200 V
Floating PWM Input
V
IH
Logic high input threshold voltage 2.3 1.9 -
V
IL
Logic low input threshold voltage - 1.9 1.5
V
I
IN+
Logic “1” input bias current - - 40 V
IN
=3.3 V
I
IN-
Logic “0” input bias current - - 1
µA
V
IN
= V
SS
Protection
V
REF
Reference output voltage 4.8 5.1 5.4 I
OREF
=0.5 mA
V
th,OCL
Low-side OC threshold in V
S
1.1 1.2 1.3 OCSET=1.2 V, Fig. 3
V
th,OCH
High-side OC threshold in V
CSH
1.1+ V
S
1.2+ V
S
1.3+ V
S
V
S
=200 V, Fig. 4
V
th,1
CSD pin shutdown release threshold 0.62 x V
DD
0.70 x V
DD
0.78 x V
DD
V
th,2
CSD pin self reset threshold 0.26 x V
DD
0.30 x V
DD
0.34 x V
DD
V
V
SS
=0 V
I
CSD+
CSD pin discharge current 70 100 130
I
CSD-
CSD pin charge current 70 100 130
µA V
SD
= V
SS
+5 V
t
SD
Shutdown propagation delay from
V
CSD
> V
SS
+ V
th,OCH
to shutdown
- - 250 Fig. 2
t
OCH
Propagation delay time from V
CSH
>
V
th,OCH
to shutdown
- - 500 Fig. 4
t
OCL
Propagation delay time from V
S
>
V
th,OCL
to shutdown
- - 500
ns
Fig. 3
Gate Driver
I
o+
Output high short circuit current
(source)
- 1.0 - V
O
=0 V, PW<10 µs
I
o-
Output low short circuit current (sink) - 1.2 -
A
V
O
=12 V, PW<10 µs
V
OL
Low level output voltage
LO – COM, HO – VS
- - 0.1 V
