NCP3126
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19
I
ICinrush_RMS
1 +
V
IN
CIN
ESR
ȧ
ȧ
ȡ
Ȣ
1 *
1
e
ƪ
t
DELAY_TOTAL
CIN
ESR
C
IN
ƫ
ȧ
ȧ
ȣ
Ȥ
(eq. 48)
0.316
5 0.1 W 330 mF
16.45 ms
0.316
5 CIN
ESR
C
IN
t
DELAY_TOTAL
380 mA +
12 V
0.1 W
ȧ
ȡ
Ȣ
1 *
1
e
ƪ
16.45 ms
0.1W 330 mF
ƫ
ȧ
ȣ
Ȥ
C
IN
= Output capacitor
CIN
ESR
= Output capacitor ESR
t
DELAY_TOTAL
= Total delay interval
V
IN
= Input voltage
Once the t
DELAY_TOTAL
has expired, the buck converter
starts to switch and a second inrush current can be
calculated:
I
OCinrush_RMS
+
ǒ
C
OUT
) C
LOAD
Ǔ
V
OUT
t
SS
D
3
Ǹ
) I
CL
D
(eq. 49)
C
OUT
= Total converter output capacitance
C
LOAD
= Total load capacitance
D = Duty ratio of the load
I
CL
= Applied load at the output
I
OCinrush_RMS
= RMS inrush current during startup
t
SS
= Softstart interval
V
OUT
= Output voltage
From the above equation, it is clear that the inrush current
is dependant on the type of load that is connected to the
output. Two types of load are considered in Figure 27: a
resistive load and a stepped current load.
NCP3126
Load
OR
Inrush Current
Figure 27. Load Connected to the Output Stage
If the load is resistive in nature, the output current will
increase with softstart linearly which can be quantified in
Equation 50.
I
CLR
_RMS +
1
3
Ǹ
V
OUT
R
OUT
(eq. 50)
191 mA +
1
3
Ǹ
3.3 V
10 W
I
CR_PK
+
V
OUT
R
OUT
330 mA +
3.3 V
10 W
R
OUT
= Output resistance
V
OUT
= Output voltage
I
CLR_RMS
= RMS resistor current
I
CR_PK
= Peak resistor current
NCP3126
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20
tss
Output
Current
Output
Voltage
3.3 V
Figure 28. Resistive Load Current
Alternatively, if the output has an under voltage lockout,
turns on at a defined voltage level, and draws a consistent
current, then the RMS connected load current is:
I
CLI+
V
OUT
* V
OUT_TO
V
OUT
Ǹ
I
OUT
(eq. 51)
798 mA +
ǒ
ǒ
3.3 V * 1.2 V
Ǔ
3.3 V
Ǔ
Ǹ
1A
I
OUT
= Output current
V
OUT
= Output voltage
V
OUT_TO
= Output voltage load turn on
tss
t
1.0 V
3.3 V
Output
Current
Output
Voltage
Figure 29. Voltage Enable Load Current
If the inrush current is higher than the steady state input
current during max load, then an input fuse should be rated
accordingly using I
2
t methodology.
Layout Considerations
As in any high frequency switching regulator, layout is
very important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. The interconnecting impedances should be
minimized by using wide short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding. For optimal performance, the NCP3126 should
have a layout similar to the one shown in Figure 30. An
important note is that the input voltage to the NCP3126
should have local decoupling to PGND. The recommended
decoupling for input voltage is a 1 mF general purpose
ceramic capacitor and a 0.01 mF COG ceramic capacitor
placed in parallel.
Top
Bottom
AGND
COG
0.01 uF
1.0 uF
RF
R2
RC
PGND
ISET
FB
COMP
AGND
BST
VIN
PGND
VSW
RISET
R1
CF
CP
CC
Single Point
Grounding
AGND
COG
0.01 uF
1.0 uF
RF
R1
RC
PGND
ISET
FB
COMP
AGND
BST
VIN
PGND
VSW
RISET
R2
CF
CP
CC
Figure 30. Recommended Layout
The typical applications are shown in Figures 31
and NO TAG for output electrolytic and ceramic bulk
capacitors, respectively.
NCP3126
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21
Figure 31. Standard Application 12 V to 2.5 V 3 A
Vin
Vout
LOUT
6.8uH
C1
10uF
16V
D1
MMSD4148T1G
C4
22uF
6.3V
R1
21.5k
R2
10k
C10
1uF
16V
R3
10R
CBST
10nF
25V
CF
180pF
10V
VIN
GND_IN
VOUT
GND
C11
0.01uF
16V
RSET
39k
VSW
FB
BST
CC
56n
10V
CP
1.8nF
50V
RC
2.1k
C9
1nF
50V
R9
100R
COMP
1
2
3
4
8
7
6
5
U1
NCP3126
RF
20k
C7
470uF
6.3V
CHF
820pF
6.3V
C3
470uF
16V
GND
PGND
FB
COMP
AGND
VSW
ISET
VIN
BST

NCP3126CRAGEVB

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Power Management IC Development Tools NCP3126 CERAMIC EVB
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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