13
LT1640AL/LT1640AH
+
V
EE
V
DD
LT1640AL
SENSE
C1
C3
Q1
R2
R3
C2
R4
R5
R6
R1
4
3
2
OV
GND
GND
–48V
UV
56
8
1
7
GATE
ACTIVE LOW
ENABLE MODULE
V
OUT
+
V
OUT
–
V
IN
+
1640A F12
V
IN
–
PWRGD
DRAIN
V
PG
V
EE
Q2
ON/OFF
–
+
(SHORT PIN)
*
* DIODES INC. SMAT70A
43
21
+
–
Figure 12. Active Low Enable Module
When the DRAIN voltage of the LT1640AL is high with
respect to V
EE
, the internal pull-down transistor Q2 is off
and the PWRGD pin is in a high impedance state (Fig-
ure␣ 12). The PWRGD pin will be pulled high by the module’s
internal pull-up current source, turning the module off.
When the DRAIN voltage drops below V
PG
, Q2 will turn on
and the PWRGD pin will pull low, enabling the module.
The PWRGD signal can also be used to turn on an LED or
optoisolator to indicate that the power is good as shown
in Figure 13.
Gate Pin Voltage Regulation
When the supply voltage to the chip is more than 15.5V,
the GATE pin voltage is regulated at 13.5V above V
EE
. If the
supply voltage is less than 15.5V, the GATE voltage will be
about 2V below the supply voltage. At the minimum 10V
supply voltage, the gate voltage is guaranteed to be greater
than 6V. The gate voltage will be no greater than 18V for
supply voltages up to 80V.
Drain Pin Protection
A unique feature of the LT1640A is the ruggedness of the
DRAIN pin. The DRAIN is designed to withstand negative
voltages (with respect to V
EE
) without requiring an exter-
nal diode. A short circuit on the –48V backplane pulls up
the V
EE
pin, but due to the storage capacitor C3 (Fig-
ure␣ 12), the DRAIN pin is held more negative than the V
EE
pin. The body diode of Q1, plus the I • R drop across R1 (if
R1 is small), holds the DRAIN pin to less than 1.5V below
V
EE
. A 1.5V reverse voltage gives rise to a 50mA reverse
drain current, which is within the design capability of the
LT1640A. A design with R1 larger than 0.1Ω may require
a resistor in series with the DRAIN pin to not exceed the
50mA drain current maximum.
APPLICATIO S I FOR ATIO
WUUU
