4
LT1640AL/LT1640AH
Gate Voltage vs Temperature
TEMPERATURE (°C)
12.0
GATE VOLTAGE (V)
13.0
14.0
15.0
12.5
13.5
14.5
–25 0 75
1640A G04
100–50 25 50
V
DD
= 48V
TEMPERATURE (°C)
–50
48
TRIP VOLTAGE (mV)
49
51
52
53
55
250
50
1640A G05
50
54
100
–25
75
TEMPERATURE (°C)
–50
GATE PULL-UP CURRENT (µA)
48
47
46
45
44
43
42
41
40
75
1640A G06
25 10050250
V
GATE
= 0V
Gate Pull-Up Current
vs Temperature
Gate Pull-Down Current
vs Temperature
TEMPERATURE (°C)
–50
GATE PULL-DOWN CURRENT (mA)
49
52
55
75
1640A G07
46
43
40
–25 0
25
50
100
V
GATE
= 2V
PWRGD Output Low Voltage
vs Temperature (LT1640AL)
TEMPERATURE (°C)
–50
PWRGD OUTPUT LOW VOLTAGE (V)
0.3
0.4
0.5
75
1640A G08
0.2
0.1
0
–25 25
0
50
100
I
OUT
= 1mA
TEMPERATURE (°C)
–50
2
OUTPUT IMPEDANCE (k)
3
4
5
6
7
8
–25 2505075
1640A G09
100
V
DRAIN
– V
EE
> 2.4V
PWRGD Output Impedance
vs Temperature (LT1640AH)
Circuit Breaker Trip Voltage
vs Temperature
When the DRAIN pin of the LT1640AH is above V
EE
by
more than V
PG
, the PWRGD pin will sink current to the
DRAIN pin which pulls the module’s enable pin low,
forcing it off. When V
DRAIN
drops below V
PG
, the PWRGD
sink current is turned off and a 6.5k resistor is connected
between PWRGD and DRAIN, allowing the module’s pull-
up current to pull the enable pin high and turn on the
module.
PWRGD/PWRGD (Pin 1): Power Good Output Pin. This pin
will toggle when V
DRAIN
is within V
PG
of V
EE
. This pin can
be connected directly to the enable pin of a power module.
When the DRAIN pin of the LT1640AL is above V
EE
by
more than V
PG
, the PWRGD pin will be high impedance,
allowing the pull-up current of the module’s enable pin to
pull the pin high and turn the module off. When V
DRAIN
drops below V
PG
, the PWRGD pin sinks current to V
EE
,
pulling the enable pin low and turning on the module.
UU
U
PI FU CTIO S
TYPICAL PERFOR A CE CHARACTERISTICS
UW
5
LT1640AL/LT1640AH
PIN FUNCTIONS
UUU
OV
(Pin 2): Analog Overvoltage Input. When OV is pulled
above the 1.223V low-to-high threshold, an overvoltage
condition is detected and the GATE pin will be immediately
pulled low. The GATE pin will remain low until OV drops
below the 1.203V high-to-low threshold.
UV (Pin 3): Analog Undervoltage Input. When UV is
pulled below the 1.223V high to low threshold, an under-
voltage condition is detected and the GATE pin will be
immediately pulled low. The GATE pin will remain low
until UV rises above the 1.243 low-to-high threshold.
The UV pin is also used to reset the electronic circuit
breaker. If the UV pin is cycled low and high following the
trip of the circuit breaker, the circuit breaker is reset and
a normal power-up sequence will occur.
V
EE
(Pin 4): Negative Supply Voltage Input. Connect to
the lower potential of the power supply.
SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense
resistor placed in the supply path between V
EE
and
SENSE, the circuit breaker will trip when the voltage
across the resistor exceeds 50mV. Noise spikes of less
than 2µs are filtered out and will not trip the circuit
breaker.
If the circuit breaker trip current is set to twice the normal
operating current, only 25mV is dropped across the
sense resistor during normal operation. To disable the
circuit breaker, V
EE
and SENSE can be shorted together.
GATE (Pin 6): Gate Drive Output for the External
N-Channel. The GATE pin will go high when the following
start-up conditions are met: the UV pin is high, the OV pin
is low and (V
SENSE
– V
EE
) < 50mV. The GATE pin is pulled
high by a 45µA current source and pulled low with a
50mA current source.
DRAIN (Pin 7): Analog Drain Sense Input. Connect this
pin to the drain of the external N-channel and the V
pin
of the power module. When the DRAIN pin is below V
PG
,
the PWRGD or PWRGD pin will toggle. In some condi-
tions, the DRAIN pin is pulled below V
EE
. The part is not
damaged if the reverse DRAIN pin current is limited to
50mA.
V
DD
(Pin 8): Positive Supply Voltage Input. Connect this
pin to the higher potential of the power supply inputs and
the V
+
pin of the power module. The input supply voltage
ranges from 10V to 80V.
BLOCK DIAGRA
W
+
+
+
+
DRAIN
1640A BD
GATESENSEV
EE
V
EE
V
PG
OUTPUT
DRIVE
PWRGD/PWRGD
50mV
V
CC
V
DD
REF
REF
UV
OV
LOGIC
AND
GATE DRIVE
V
CC
AND
REFERENCE
GENERATOR
+
+
6
LT1640AL/LT1640AH
PWRGD/PWRGD V
DD
V
+
5V
OV
V
DRAIN
48V
R
5k
DRAIN
LT1640AL/LT1640AH
UV GATE
V
EE
SENSE
V
SENSE
1640A F01
V
UV
V
OV
+
Figure 1. Test Circuit
2V
1V
1640A F02
t
PHLOV
1.223V
0V
OV
GATE
1V
1.203V
t
PLHOV
TIMING DIAGRAMS
WUW
Figure 2. OV to GATE Timing
2V
1V
1640A F03
t
PHLUV
1.223V
0V
UV
GATE
1V
1.243V
t
PLHUV
Figure 3. UV to GATE Timing
Figure 4. SENSE to GATE Timing
1V
1640A F04
t
PHLSENSE
50mV
SENSE
GATE
1.8V
1V
1640A F05
0V
V
PWRGD
– V
DRAIN
= 0V
DRAIN
PWRGD
1V
1.4V
1.8V
1V
t
PLHPG
V
EE
V
EE
DRAIN
PWRGD
1V
1.4V
t
PHLPG
t
PLHPG
t
PHLPG
Figure 5. DRAIN to PWRGD/PWRGD Timing
TEST CIRCUIT

LT1640ALIS8#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Hot Swap Controller for -48V
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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