AD7401AYRWZ-RL Datasheet ADW70015Z-0RL, AD7401AYRWZ-RL, AD7401AYRWZ | P16-P18

AD7401A

Rev. C | Page 15 of 20

DIFFERENTIAL INPUTS

The analog input to the modulator is a switched capacitor

design. The analog signal is converted into charge by highly

linear sampling capacitors. A simplified equivalent circuit

diagram of the analog input is shown in Figure 24. A signal

source driving the analog input must be able to provide the

charge onto the sampling capacitors every half MCLKIN cycle

and settle to the required accuracy within the next half cycle.

φA

φB

1kΩ

–

φA

φB

φB φB

1kΩ

2pF

φA φA

MCLKIN

7332-024

Figure 24. Analog Input Equivalent Circuit

Because the AD7401A samples the differential voltage across

its analog inputs, low noise performance is attained with an

input circuit that provides low common-mode noise at each

input. The amplifiers used to drive the analog inputs play a

critical role in attaining the high performance available from the

AD7401A.

When a capacitive load is switched onto the output of an op

amp, the amplitude momentarily drops. The op amp tries to

correct the situation and, in the process, hits its slew rate limit.

This nonlinear response, which can cause excessive ringing,

can lead to distortion. To remedy the situation, a low-pass RC

filter can be connected between the amplifier and the input

to the AD7401A. The external capacitor at each input aids

in supplying the current spikes created during the sampling

process, and the resistor isolates the op amp from the transient

nature of the load.

The recommended circuit configuration for driving the

differential inputs to achieve best performance is shown in

Figure 25. A capacitor between the two input pins sources or

sinks charge to allow most of the charge that is needed by one

input to be effectively supplied by the other input. The series

resistor again isolates any op amp from the current spikes

created during the sampling process. Recommended values for

the resistors and capacitor are 22 Ω and 47 pF, respectively.

–

AD7401A

07332-025

Figure 25. Differential Input RC Network

CURRENT SENSING APPLICATIONS

The AD7401A is ideally suited for current sensing applications

where the voltage across a shunt resistor is monitored. The load

current flowing through an external shunt resistor produces a

voltage at the input terminals of the AD7401A. The AD7401A

provides isolation between the analog input from the current

sensing resistor and the digital outputs. By selecting the appro-

priate shunt resistor value, a variety of current ranges can be

monitored.

Choosing R

SHUNT

The shunt resistor values used in conjunction with the AD7401A

are determined by the specific application requirements in

terms of voltage, current, and power. Small resistors minimize

power dissipation, while low inductance resistors prevent any

induced voltage spikes, and good tolerance devices reduce

current variations. The final values chosen are a compromise

between low power dissipation and good accuracy. Low value

resistors have less power dissipated in them, but higher value

resistors may be required to utilize the full input range of the

ADC, thus achieving maximum SNR performance.

When the peak sense current is known, the voltage range of the

AD7401A (±200 mV) is divided by the maximum sense current

to yield a suitable shunt value. If the power dissipation in the

shunt resistor is too large, the shunt resistor can be reduced

and less of the ADC input range is used. Using less of the ADC

input range results in performance that is more susceptible to

noise and offset errors because offset errors are fixed and are

thus more significant when smaller input ranges are used.

SHUNT

must be able to dissipate the I2R power losses. If the

power dissipation rating of the resistor is exceeded, its value

may drift or the resistor may be damaged, resulting in an open

circuit. This can result in a differential voltage across the ter-

minals of the AD401A in excess of the absolute maximum

ratings. If I

SENSE

has a large high frequency component, take

care to choose a resistor with low inductance.

VOLTAGE SENSING APPLICATIONS

The AD7401A can also be used for isolated voltage monitoring.

For example, in motor control applications, it can be used to

sense bus voltage. In applications where the voltage being moni-

tored exceeds the specified analog input range of the AD7401A,

a voltage divider network can be used to reduce the voltage to

be monitored to the required range.

AD7401A

Rev. C | Page 16 of 20

DIGITAL FILTER

The overall system resolution and throughput rate is determined

by the filter selected and the decimation rate used. The higher

the decimation rate, the greater the system accuracy, as illus-

trated in Figure 26. However, there is a tradeoff between accuracy

and throughput rate and, therefore, higher decimation rates

result in lower throughput solutions. Note that for a given

bandwidth requirement, a higher MCLKIN frequency can allow

for higher decimation rates to be used, resulting in higher SNR

performance.

10 100 1k1

DECIMATION RATE

SNR (dB)

SINC3

SINC2

SINC1

07332-026

Figure 26. SNR vs. Decimation Rate for Different Filter Types

A sinc3 filter is recommended for use with the AD7401A. This

filter can be implemented on an FPGA or a DSP.

(

)

()

)(

⎟

⎠

⎞

⎜

⎝

⎛

−

where DR is the decimation rate.

The following Verilog code provides an example of a sinc3 filter

implementation on a Xilinx® Spartan-II 2.5 V FPGA. This code

can possibly be compiled for another FPGA, such as an Altera®

device. Note that the data is read on the negative clock edge in

this case, although it can be read on the positive edge, if

preferred.

/*`Data is read on negative clk edge*/

module DEC256SINC24B(mdata1, mclk1, reset,

DATA);

input mclk1; /*used to clk filter*/

input reset; /*used to reset filter*/

input mdata1; /*ip data to be

filtered*/

output [15:0] DATA; /*filtered op*/

integer location;

integer info_file;

reg [23:0] ip_data1;

reg [23:0] acc1;

reg [23:0] acc2;

reg [23:0] acc3;

reg [23:0] acc3_d1;

reg [23:0] acc3_d2;

reg [23:0] diff1;

reg [23:0] diff2;

reg [23:0] diff3;

reg [23:0] diff1_d;

reg [23:0] diff2_d;

reg [15:0] DATA;

reg [7:0] word_count;

reg word_clk;

reg init;

/*Perform the Sinc ACTION*/

always @ (mdata1)

if(mdata1==0)

ip_data1 <= 0; /* change from a 0

to a -1 for 2's comp */

else

ip_data1 <= 1;

/*ACCUMULATOR (INTEGRATOR)

Perform the accumulation (IIR) at the speed

of the modulator.

MCLKIN

IP_DATA1

ACC1+ ACC2+

ACC3+

07332-027

Figure 27. Accumulator

AD7401A

Rev. C | Page 17 of 20

Z = one sample delay

MCLKOUT = modulators conversion bit rate

Z = one sample delay

WORD_CLK = output word rate

always @ (posedge mclk1 or posedge reset)

if (reset)

begin

/*initialize acc registers on reset*/

acc1 <= 0;

acc2 <= 0;

acc3 <= 0;

end

else

begin

/*perform accumulation process*/

acc1 <= acc1 + ip_data1;

acc2 <= acc2 + acc1;

acc3 <= acc3 + acc2;

end

always @ (posedge word_clk or posedge reset)

if(reset)

begin

acc3_d2 <= 0;

diff1_d <= 0;

diff2_d <= 0;

diff1 <= 0;

diff2 <= 0;

diff3 <= 0;

end

else

begin

diff1 <= acc3 - acc3_d2;

diff2 <= diff1 - diff1_d;

diff3 <= diff2 - diff2_d;

acc3_d2 <= acc3;

diff1_d <= diff1;

diff2_d <= diff2;

end

/*DECIMATION STAGE (MCLKOUT/ WORD_CLK)

always @ (negedge mclk1 or posedge reset)

if (reset)

word_count <= 0;

else

word_count <= word_count + 1;

/* Clock the Sinc output into an output

word_clk <= word_count[7];

/*DIFFERENTIATOR ( including decimation

stage)

Perform the differentiation stage (FIR) at a

lower speed.

WORD_CLK

DATADIFF3

07332-029

Figure 29. Clocking Sinc Output into an Output Register

ORD_CLK

ACC3

DIFF1

DIFF3

–

DIFF2

–1

–

–1

07332-028

WORD_CLK = output word rate

always @ (posedge word_clk)

begin

Figure 28. Differentiator

DATA[15] <= diff3[23];

DATA[14] <= diff3[22];

DATA[13] <= diff3[21];

DATA[12] <= diff3[20];

DATA[11] <= diff3[19];

DATA[10] <= diff3[18];

DATA[9] <= diff3[17];

DATA[8] <= diff3[16];

DATA[7] <= diff3[15];

DATA[6] <= diff3[14];

DATA[5] <= diff3[13];

DATA[4] <= diff3[12];

DATA[3] <= diff3[11];

DATA[2] <= diff3[10];

DATA[1] <= diff3[9];

DATA[0] <= diff3[8];

end

endmodule

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AD7401AYRWZ-RL

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Analog to Digital Converters - ADC Isolated Modulator

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