AD7401A
Rev. C | Page 3 of 20
SPECIFICATIONS
V
DD1
= 4.5 V to 5.5 V, V
DD2
= 3 V to 5.5 V, V
IN
+ = −200 mV to +200 mV, and V
IN
− = 0 V (single-ended); T
A
= −40°C to +125°C, f
MCLKIN
=
16 MHz maximum,
1
tested with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted.
Table 1.
Y Version
1, 2
Parameter
Min Typ Max
Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution
16 Bits Filter output truncated to 16 bits
Integral Nonlinearity (INL)
3
±1.5 ±7 LSB
V
IN
+ = ±200 mV, T
A
= −40°C to +85°C, f
MCLKIN
= 20 MHz max
1
±2 ±13 LSB
V
IN
+ = ±250 mV, T
A
= −40°C to +85°C, f
MCLKIN
= 20 MHz max
1
±1.5 ±11 LSB
V
IN
+ = ±200 mV, T
A
= −40°C to +125°C, f
MCLKIN
= 20 MHz max
1
±2 ±46 LSB
V
IN
+ = ±250 mV, T
A
= −40°C to +125°C, f
MCLKIN
= 20 MHz max
1
Differential Nonlinearity (DNL)
3
±0.9 LSB Guaranteed no missed codes to 16 bits,
f
MCLKIN
= 20 MHz max,
1
V
IN
+ = −250 mV to +250 mV
Offset Error
3
±.025 ±0.5 mV
f
MCLKIN
= 20 MHz max,
1
V
IN
+ = −250 mV to +250 mV
Offset Drift vs. Temperature
3
1 3.5 μV/°C
Offset Drift vs. V
DD1
3
120 μV/V
Gain Error
3
0.07 ±1.5 mV
±1 mV
f
MCLKIN
= 20 MHz max,
1
V
IN
+ = −250 mV to +250 mV
Gain Error Drift vs. Temperature
3
23 μV/°C
Gain Error Drift vs. V
DD1
3
110 μV/V
ANALOG INPUT
Input Voltage Range
±200 ±250 mV For specified performance; full range ±320 mV
Dynamic Input Current ±13 ±18 μA
V
IN
+ = 500 mV, V
IN
− = 0 V, f
MCLKIN
= 20 MHz max
1
±10 ±15 μA
V
IN
+ = 400 mV, V
IN
− = 0 V, f
MCLKIN
= 20 MHz max
1
0.08 μA
V
IN
+ = 0 V, V
IN
− = 0 V, f
MCLKIN
= 20 MHz max
1
DC Leakage Current ±0.01 ±0.6 μA
Input Capacitance 10 pF
DYNAMIC SPECIFICATIONS V
IN
+ = 5 kHz
Signal-to-(Noise + Distortion) Ratio (SINAD)
3
76 82 dB V
IN
+ = ±200 mV, T
A
= −40°C to +85°C,
f
MCLKIN
= 5 MHz to 20 MHz
1
71 82 dB V
IN
+ = ±250 mV, T
A
= −40°C to +85°C,
f
MCLKIN
= 5 MHz to 20 MHz
1
72 82 dB V
IN
+ = ±200 mV, T
A
= −40°C to +125°C,
f
MCLKIN
= 5 MHz to 20 MHz
1
82 dB V
IN
+ = ±250 mV, T
A
= −40°C to +125°C,
f
MCLKIN
= 5 MHz to 20 MHz
1
Signal-to-Noise Ratio (SNR)
3
81 83 dB V
IN
+ = ±250 mV, T
A
= −40°C to +125°C,
f
MCLKIN
= 5 MHz to 20 MHz
1
80 82 dB V
IN
+ = ±200 mV, T
A
= −40°C to +125°C,
f
MCLKIN
= 5 MHz to 20 MHz
1
Total Harmonic Distortion (THD)
3
−90 dB
f
MCLKIN
= 20 MHz max
1
, V
IN
+ = −250 mV to +250 mV
Peak Harmonic or Spurious Noise (SFDR)
3
−92 dB
Effective Number of Bits (ENOB)
3
12.3 13.3 Bits
Isolation Transient Immunity
3
25 30 kV/μs
LOGIC INPUTS
Input High Voltage, V
IH
0.8 × V
DD2
V
Input Low Voltage, V
IL
0.2 × V
DD2
V
Input Current, I
IN
±0.5 μA
Floating State Leakage Current 1 μA
Input Capacitance, C
IN
4
10 pF
AD7401A
Rev. C | Page 4 of 20
Y Version
1, 2
Parameter
Min Typ Max
Unit Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DD2
− 0.1 V I
O
= −200 μA
Output Low Voltage, V
OL
0.4 V I
O
= +200 μA
POWER REQUIREMENTS
V
DD1
4.5 5.5 V
V
DD2
3 5.5 V
I
DD1
5
10 12 mA V
DD1
= 5.5 V
I
DD2
6
7 9 mA V
DD2
= 5.5 V
3 4 mA V
DD2
= 3.3 V
POWER DISSIPATION (SEE Figure 17)
93.5 MW V
DD1
= V
DD2
= 5.5 V
1
For f
MCLK
> 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, V
DD1
= V
DD2
= 5 V ± 5%, and T
A
= −40°C to +85°C.
2
All voltages are relative to their respective ground.
3
See the section. Terminology
4
Sample tested during initial release to ensure compliance.
5
See . Figure 15
6
See . Figure 17
AD7401A
Rev. C | Page 5 of 20
TIMING SPECIFICATIONS
V
DD1
= 4.5 V to 5.5 V, V
DD2
= 3 V to 5.5 V, T
A
= −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
1
Limit at T
MIN
, T
MAX
Unit Description
f
MCLKIN
2, 3
20 MHz max Master clock input frequency
5 MHz min Master clock input frequency
t
1
4
25 ns max Data access time after MCLKIN rising edge
t
2
4
15 ns min Data hold time after MCLKIN rising edge
t
3
0.4 × t
MCLKIN
ns min Master clock low time
t
4
0.4 × t
MCLKIN
ns min Master clock high time
1
Sample tested during initial release to ensure compliance.
2
Mark space ratio for clock input is 40/60 to 60/40 for f
MCLKIN
≤ 16 MHz and 48/52 to 52/48 for 16 MHz < f
MCLKIN
< 20 MHz.
3
V
DD1
= V
DD2
= 5 V ± 5% for f
MCLKIN
> 16 MHz to 20 MHz.
4
Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.0 V. Figure 2
200µA I
OL
200µA I
OH
1.6V
TO OUTPUT
PIN
C
L
25pF
07332-002
Figure 2. Load Circuit for Digital Output Timing Specifications
MCLKIN
MDAT
t
1
t
2
t
4
t
3
07332-003
Figure 3. Data Timing

AD7401AYRWZ-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Isolated Modulator
Lifecycle:
New from this manufacturer.
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