16
LTC3720
3720f
External Gate Drive Buffers
The LTC3720 drivers are adequate for driving up to about
60nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating at
higher frequencies requiring greater RMS currents will
benefit from using external gate drive buffers such as the
LTC1693. Alternately, the external buffer circuit shown in
Figure 5 can be used. Note that the bipolar devices reduce
the signal swing at the MOSFET gate and benefit from an
increased EXTV
CC
voltage of about 6V.
APPLICATIO S I FOR ATIO
WUUU
3.3V OR 5V RUN/SS
V
IN
INTV
CC
RUN/SS
D1
(6a) (6b)
D2*
C
SS
R
SS
*
C
SS
*OPTIONAL TO OVERRIDE
OVERCURRENT LATCHOFF
R
SS
*
3720 F06
Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated
back until the output reaches 75% of its final value. The pin
can be driven from logic as shown in Figure 6. Diode D1
reduces the start delay while allowing C
SS
to charge up
slowly for the soft-start function.
After the controller has been started and given adequate
time to charge up the output capacitor, C
SS
is used as a
short-circuit timer. After the RUN/SS pin charges above
4V, if the output voltage falls below 75% of its regulated
value, then a short-circuit fault is assumed. A 1.8µA cur-
rent then begins discharging C
SS
. If the fault condition
persists until the RUN/SS pin drops to 3.5V, then the con-
troller turns off both power MOSFETs, shutting down the
converter permanently. The RUN/SS pin must be actively
pulled down to ground in order to restart operation.
The overcurrent protection timer requires that the soft-
start timing capacitor C
SS
be made large enough to guar-
antee that the output is in regulation by the time C
SS
has
reached the 4V threshold. In general, this will depend upon
the size of the output capacitance, output voltage and load
current characteristic. A minimum soft-start capacitor can
be estimated from:
C
SS
> C
OUT
V
OUT
R
SENSE
(10
–4
[F/V s])
Generally 0.1µF is more than sufficient.
Overcurrent latchoff operation is not always needed or
desired. Load current is already limited during a short-
circuit by the current foldback circuitry and latchoff
Figure 5. Optional External Gate Driver
Q1
FMMT619
GATE
OF M1
TG
BOOST
SW
Q2
FMMT720
Q3
FMMT619
GATE
OF M2
BG
10
3720 F05
INTV
CC
PGND
Q4
FMMT720
10
Soft-Start and Latchoff with the RUN/SS Pin
The RUN/SS pin provides a means to shut down the
LTC3720 as well as a timer for soft-start and overcurrent
latchoff. Pulling the RUN/SS pin below 0.8V puts the
LTC3720 into a low quiescent current shutdown
(I
Q
< 30µA). Releasing the pin allows an internal 1.2µA
current source to charge up the external timing capacitor
C
SS
. If RUN/SS has been pulled all the way to ground,
there is a delay before starting of about:
t
V
A
CsFC
DELAY SS SS
=
µ
()
15
12
13
.
.
./
When the voltage on RUN/SS reaches 1.5V, the LTC3720
begins operating with a clamp on I
TH
of approximately
0.9V. As the RUN/SS voltage rises to 3V, the clamp on I
TH
is raised until its full 2.4V range is available. This takes an
additional 1.3s/µF, during which the load current is folded
17
LTC3720
3720f
operation can prove annoying during troubleshooting.
The feature can be overridden by adding a pull-up current
greater than 5µA to the RUN/SS pin. The additional
current prevents the discharge of C
SS
during a fault and
also shortens the soft-start period. Using a resistor to V
IN
as shown in Figure 6a is simple, but slightly increases
shutdown current. Connecting a resistor to INTV
CC
as
shown in Figure 6b eliminates the additional shutdown
current, but requires a diode to isolate C
SS
. Any pull-up
network must be able to pull RUN/SS above the 4.5V
maximum threshold that arms the latchoff circuit and
overcome the 4µA maximum discharge current.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3720 circuits:
1. DC I
2
R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same R
DS(ON)
, then the
resistance of one MOSFET can simply be summed with the
resistances of L and the board traces to obtain the DC I
2
R
loss. For example, if R
DS(ON)
= 0.01 and R
L
= 0.005, the
loss will range from 1% up to 10% as the output current
varies from 1A to 10A for a 1.5V output.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capaci-
tance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:
Transition Loss (1.7A
–1
) V
IN
2
I
OUT
C
RSS
f
APPLICATIO S I FOR ATIO
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3. INTV
CC
current. This is the sum of the MOSFET driver
and control currents. This loss can be reduced by supply-
ing INTV
CC
current through the EXTV
CC
pin from a high
efficiency source, such as an output derived boost net-
work or alternate supply if available.
4. C
IN
loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I
2
R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Other losses, including C
OUT
ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to I
LOAD
(ESR), where ESR is the effective series
resistance of C
OUT
. I
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used
by the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability
problem. The I
TH
pin external components shown in
Figure 7 will provide adequate compensation for most
applications. For a detailed explanation of switching
control loop theory see Application Note 76.
18
LTC3720
3720f
Design Example
As a design example, take a supply with the following
specifications: V
IN
= 7V to 24V (15V nominal), V
OUT
= 1.05V
to 1.825V with typical at 1.5V, I
OUT(MAX)
= 15A, f = 300kHz.
First, calculate the timing resistor with V
ON
= V
OUT
:
R
kHz pF
k
ON
=
()()
=
1
300 10
330
and choose the inductor for about 40% ripple current at
the maximum V
IN
:
L
V
kHz A
V
V
H=
()()()
15
300 0 4 15
1
15
24
08
.
.
.
.
Selecting a standard value of 1µH results in a maximum
ripple current of:
∆=
()
µ
()
=I
V
kHz H
V
V
A
L
15
300 1
1
15
24
47
.
.
.
Next, choose the synchronous MOSFET switch. Because
of the narrow duty cycle and large current, a single SO-8
MOSFET will have difficulty dissipating the power lost in the
switch. Choosing two IRF7811A (R
DS(ON)
= 0.013, C
RSS
= 60pF, θ
JA
= 50°C/W) yields a nominal sense voltage of:
V
SNS(NOM)
= (15A)(0.5)(1.3)(0.012) = 117mV
Tying V
RNG
to INTV
CC
will set the current sense voltage
range for a nominal value of 140mV with current limit
occurring at 186mV. To check if the current limit is
acceptable, assume a junction temperature of about 100°C
above a 50°C ambient with ρ
150°C
= 1.6:
APPLICATIO S I FOR ATIO
WUUU
I
mV
AA
LIMIT
()()
()
+
()
=
186
05 16 0012
1
2
47 18
...
.
and double check the assumed T
J
in the MOSFET:
P
VV
V
A
W
BOT
=
()
()
=
24 1 5
24
21 7
2
16 0012 212
2
–. .
.. .
T
J
= 50°C + (2.12W)(50°C/W) = 156°C
Because the top MOSFET is on for such a short time, a
single IRF7811A will be sufficient. Checking its power
dissipation at current limit with ρ
90°C
= 1.3:
P
V
V
A
V A pF kHz
WWW
BOT
=
()()
()
+
()( )( )( )( )
=+=
15
24
21 7 1 3 0 012
1 7 24 21 7 60 300
046 038 084
2
2
.
...
..
...
T
J
= 50°C + (0.84W)(50°C/W) = 92°C
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
C
IN
is chosen for an RMS current rating of about 6A at
temperature. The output capacitors are chosen for a low
ESR of 0.005 to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
V
OUT(RIPPLE)
= I
L(MAX)
(ESR)
= (4.7A) (0.005) = 24mV

LTC3720EGN#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Single-Phase Buck Controller
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