NBC12430, NBC12430A
http://onsemi.com
9
PROGRAMMING INTERFACE
Programming the NBC12430 and NBC12430A is
accomplished by properly configuring the internal dividers
to produce the desired frequency at the outputs. The output
frequency can by represented by this formula:
F
OUT
((F
XTAL
or F
REF_EXT
) 16) 2M N
(eq. 1)
where F
XTAL
is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that it
is possible to select values of M such that the PLL is unable
to achieve loop lock. To avoid this, always make sure that M
is selected to be 200 ≤ M ≤ 400 for a 16 MHz input reference.
Assuming that a 16 MHz reference frequency is used the
above equation reduces to:
F
OUT
2M N
(eq. 2)
Substituting the four values for N (1, 2, 4, 8) yields:
Table 10. Programmable Output Divider Function
Table
N1 N0
N
Divider
F
OUT
Output
Frequency
Range (MHz)*
F
OUT
Step
1 1 1 M 2 400−800 2 MHz
0 0 2 M 200−400 1 MHz
0 1 4 M 2 100−200 500 kHz
1 0 8 M 4 50−100 250 kHz
*For crystal frequency of 16 MHz.
The user can identify the proper M and N values for the
desired frequency from the above equations. The four output
frequency ranges established by N are 400−800 MHz,
200−400 MHz, 100−200 MHz and 50−100 MHz, respectively.
From these ranges, the user will establish the value of N
required. The value of M can then be calculated based on
equation 1. For example, if an output frequency of 131 MHz
was desired, the following steps would be taken to identify the
appropriate M and N values. 131 MHz falls within the
frequency range set by an N value of 4; thus, N [1:0] = 01.
For N = 4, F
OUT
= M ÷ 2 and M = 2 x F
OUT
. Therefore,
M = 131 x 2 = 262, so M[8:0] = 100000110. Following this
same procedure, a user can generate any whole frequency
desired between 50 and 800 MHz. Note that for N > 2,
fractional values of F
OUT
can be realized. The size of the
programmable frequency steps (and thus, the indicator of the
fractional output frequencies achievable) will be equal to
F
XTAL
÷ 16 ÷ N.
For input reference frequencies other than 16 MHz, see
Table 11, which shows the usable VCO frequency and M
divider range.
The input frequency and the selection of the feedback
divider M is limited by the VCO frequency range and
F
XTAL
. M must be configured to match the VCO frequency
range of 400 to 800 MHz in order to achieve stable PLL
operation.
M
min
f
VCOmin
2(f
XTAL
16) and
(eq. 3)
M
max
f
VCOmax
2(f
XTAL
16)
(eq. 4)
The value for M falls within the constraints set for PLL
stability. If the value for M fell outside of the valid range, a
different N value would be selected to move M in the
appropriate direction.
The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is
controlled via the P_LOAD
signal such that a LOW to HIGH
transition will latch the information present on the M[8:0]
and N[1:0] inputs into the M and N counters. When the
P_LOAD
signal is LOW, the input latches will be
transparent and any changes on the M[8:0] and N[1:0] inputs
will affect the F
OUT
output pair. To use the serial port, the
S_CLOCK signal samples the information on the S_DATA
line and loads it into a 14 bit shift register. Note that the
P_LOAD
signal must be HIGH for the serial load operation
to function. The Test register is loaded with the first three
bits, the N register with the next two, and the M register with
the final nine bits of the data stream on the S_DATA input.
For each register, the most significant bit is loaded first (T2,
N1, and M8). A pulse on the S_LOAD pin after the shift
register is fully loaded will transfer the divide values into the
counters. The HIGH to LOW transition on the S_LOAD
input will latch the new divide values into the counters.
Figures 5 and 6 illustrate the timing diagram for both a
parallel and a serial load of the device synthesizer.
M[8:0] and N[1:0] are normally specified once at
power−up through the parallel interface, and then possibly
again through the serial interface. This approach allows the
application to come up at one frequency and then change or
fine−tune the clock as the ability to control the serial
interface becomes available.
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the
parallel interface. The T2, T1, and T0 control bits are preset
to ‘000’ when P_LOAD
is LOW so that the PECL F
OUT
outputs are as jitter−free as possible. Any active signal on the
TEST output pin will have detrimental affects on the jitter
of the PECL output pair. In normal operations, jitter
specifications are only guaranteed if the TEST output is
static. The serial configuration port can be used to select one
of the alternate functions for this pin.
