LE7942B-1DJC Datasheet LE7942B-1DJCT, LE7942B-1DJC, LE7942B-2DJC | P4-P6

Le7942B Data Sheet

Zarlink Semiconductor Inc.

PIN DESCRIPTIONS

Notes:

1. All pins, except CHCLK, connect to VBAT when using SLIC without a switching regulator. CHCLK is connected to AGND/

DGND.

2. To prevent noise pickup by the detection circuits when using Ground-Key Detect state (E1 = logical 1), a 3300 pF minimum

bypass capacitor is recommended between the GKFIL pin and ground.

3. Each relay driver has a zener clamp to BGND.

Pin Names Type Description

AGND/DGND Gnd Analog and Digital ground.

A (TIP) Output Output of A(TIP) power amplifier.

BGND Gnd Battery (power) ground.

B (RING) Output Output of B(RING) power amplifier.

C3–C1 Input Decoder. TTL compatible. C3 is MSB and C1 is LSB.

C4 Input Test Relay Driver Command. TTL compatible. A logic Low enables the driver.

CAS Capacitor Anti-saturation pin for capacitor to filter reference voltage when operating in anti-saturation

region.

CHCLK Input Chopper Clock. Input to switching regulator (TTL compatible). Freq = 256 kHz (typ).

(See Note 1).

CHS Input Chopper Stabilization. (See Note 1) Connection for external chopper stabilizing components.

DA Input Ring-trip negative. Negative input to ring-trip comparator.

DB Input Ring-trip positive. Positive input to ring-trip comparator.

DET

Output Switchhook detector. When enabled, a logic Low indicates the selected detector is tripped. The

detector is selected by the logic inputs (C3–C1, E1). The output is open-collector with a built-in

15 kΩ pull-up resistor.

E1 Input Ground-Key Enable. E1 = High connects the ground-key detector to DET

. E1 = Low connects the

off-hook or ring-trip detector to DET

GKFIL — Connection for external ground-key, noise-filter capacitor. (See Note 2.)

HPA Capacitor High-Pass Filter Capacitor. A(TIP) side of high-pass filter capacitor.

HPB Capacitor High-Pass Filter Capacitor. B(RING) side of high-pass filter capacitor.

L Output

(See Note 1)

Switching Regulator Power Transistor. Connection point for filter inductor and anode of Switching

Regulator Power Transistor. Connection point for filter inductor and anode of catch diode. Has up

to 60 V of pulse waveform on it and must be isolated from sensitive circuits. Keep the diode

connections short because of the high currents and high di/dt.

QBAT Battery Quiet Battery. (See Note 1). Filtered battery supply for the signal processing circuits.

RD Resistor Detector resistor. Detector threshold set and filter pin. May be connected to ground or -5V.

RDC Resistor DC feed resistor. Connection point for the DC feed current programming network. The other end

of the network connects to the receiver summing node (RSN).

RINGOUT Output Ring Relay Driver. Open-collector driver with emitter internally connected to BGND.

(See Note 3)

RSN Input Receive Summing Node. The metallic current (AC and DC) between A(TIP) and B(RING) is equal

to 500 x the current into this pin. The networks that program receive gain, two-wire impedance,

and feed current all connect to this node.

TESTOUT Output Test Relay Driver. Open collector driver with emitter internally connected to BGND.

(See Note 3)

TP Thermal Thermal pin. Connection for heat dissipation. Internally connected to substrate (QBAT). Leave as

open circuit or connected to QBAT. In both cases, the TP pins can connect to an area of copper

on the board to enhance heat dissipation.

VBAT Battery Battery supply.

VCC Power +5 V power supply.

VBREF Power Reference voltage. No current on the pin. May be connected to QBAT or –5 V.

VREG Input Regulated Voltage. (See Note 1.) Provides negative power supply for power amplifiers.

Connection point for inductor, filter capacitor, and chopper stabilization.

VTX Output Transmit Audio. This output is a unity gain version of the A(TIP) and B(RING) metallic voltage.

VTX also sources the two-wire input impedance programming network.

Le7942B Data Sheet

Zarlink Semiconductor Inc.

ABSOLUTE MAXIMUM RATINGS

Storage temperature . . . . . . . . . . . . –55°C to +150°C

with respect to AGND/DGND . . . –0.4 V to +7.0 V

with respect to AGND/DGND . . . +0.4 V to QBAT

BAT

with respect to AGND/DGND. . . +0.4 V to –70 V

Note: Rise time of V

BAT

(dv/dt) must be limited to 27 V/µs or

less when Q

BAT

bypass = 0.33 µF.

BGND with respect to AGND/DGND .+1.0 V to –3.0 V

A(TIP) or B(RING) to BGND:

Continuous . . . . . . . . . . . . . . . . . . –70 V to +1.0 V

10 ms (f = 0.1 Hz) . . . . . . . . . . . . . –70 V to +5.0 V

1 µs (f = 0.1 Hz) . . . . . . . . . . . . . . .–90 V to +10 V

250 ns (f = 0.1 Hz) . . . . . . . . . . . .–120 V to +15 V

Current from A(TIP) or B(RING). . . . . . . . . . . .±150 mA

Voltage on RINGOUT, TESTOUT . . . . BGND to + 7 V

Voltage on RINGOUT, TESTOUT (transient)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BGND to +10 V

Current through relay drivers . . . . . . . . . . . . . . 60 mA

Voltage on ring-trip inputs

(DA and DB) . . . . . . . . . . . . . . . . . . . . . V

BAT

to 0 V

Current into ring-trip inputs . . . . . . . . . . . . . . . . .±10 mA

Peak current into regulator

switch (L pin). . . . . . . . . . . . . . . . . . . . . . . 150 mA

Switcher transient peak off

voltage on L pin. . . . . . . . . . . . . . . . . . . . . . +1.0 V

C4–C1, E1, CHCLK to

AGND/DGND . . . . . . . . . . . .–0.4 V to V

+ 0.4 V

Maximum power dissipation, T

(see note) . . . . .70°C

In 32-pin PLCC package. . . . . . . . . . . . . . . 1.74 W

Note: Thermal limiting circuitry on chip will shut down the

circuit at a junction temperature of about 165°C. The device

should never be exposed to this temperature. Operation

above 145°C junction temperature may degrade device

reliability. See the SLIC Packaging Considerations for more

information.

Stresses above those listed under Absolute Maximum Ratings

cancause permanent device failure. Functionality at or above

these limits is not implied. Exposure to Absolute Maximum

Ratings for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient temperature . . . . . . . . . . . . . . 0°C to +70°C*

. . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 V to 5.25 V

. . . . . . . . . . . . . . . . . . . . . . . . . . –4.75 V to QBAT

BAT

. . . . . . . . . . . . . . . . . . . . . . . . . . –19 V to –58 V**

AGND/DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V

BGND with respect to

AGND/DGND. . . . . . . . . . . . –100 mV to +100 mV

Load Resistance on VTX to ground . . . . . . 10 kΩ min

The Operating Ranges define those limits between which the

functionality of the device is guaranteed.

*Legerity guarantees the performance of this device over

commercial (0 to 70°C) and industrial (-40 to 85 °C)

temperature ranges by conducting electrical characterization

over each range and by conducting a production test with

single insertion coupled to periodic sampling. These

characterization and test procedures comply with section

4.6.2 of Bellcore TR-TSY-000357 Component Reliability

Assurance Requirements for Telecommunications

Equipment.

**Can be used without switching regulator components in this

range of battery voltages, provided maximum power

dissipation specifications are not exceeded.

Package Assembly

The non-green package devices are assembled with

industry-standard mold compounds, and the leads

possess a tin/lead (Sn/Pb) plating. These packages

are compatible with conventional SnPb eutectic solder

board assembly processes. The peak soldering

temperature should not exceed 225°C during printed

circuit board assembly.

The green package devices are assembled with

enhanced environmental compatible lead-free,

halogen-free, and antimony-free materials. The leads

possess a matte-tin plating which is compatible with

conventional board assembly processes or newer

lead-free board assembly processes. The peak

soldering temperature should not exceed 245°C during

printed circuit board assembly.

Refer to IPC/JEDEC J-Std-020B Table 5-2 for the

recommended solder reflow temperature profile

Le7942B Data Sheet

Zarlink Semiconductor Inc.

ELECTRICAL CHARACTERISTICS

Description Test Conditions (See Note 1) Grade Min Typ Max Unit Note

Analog (V

) output impedance all 3 — Ω 4

Analog (V

) output offset 0°C to +70°C

–1

–2

–35

–30

—

+35

+30

—

–40°C to +85°C

–1

–2

–40

–35

—

+40

+35

Analog (RSN) input impedance 300 Hz to 3.4 kHz all — 1 20

Ω

—

Longitudinal impedance at A or

all — — 35 —

Overload level 4-wire

2-wire

all –2.5 — +2.5 Vpk 2

Transmission Performance, 2-Wire Impedance (See Test Circuit D)

2-wire return loss 300 to 3400 Hz all 26 — — dB 4, 10

Longitudinal Balance (2-Wire and 4-Wire, See Test Circuit C); R

= 600 Ω

Longitudinal to metallic L-T, L-4

200 Hz to 1 kHz

normal polarity 0°C to +70°C

normal polarity –40°C to +85°C

reverse polarity

–1

–2

——

1, 2

1, 2, 4

1, 2

1 kHz to 3.4 kHz

normal polarity 0°C to +70°C

normal polarity –40°C to +85°C

reverse polarity

–1

–2

——

1, 2

1, 2, 4

1, 2

Longitudinal signal generation

4-L

300 Hz to 800 Hz

Reverse polarity –1

–2

——

Longitudinal current capability

per wire

Active state

OHT state

all —

— mArms 4

Insertion Loss (4- to 2-Wire, See Test Circuit B)

BAT = –48 V, R

LDC

= R

LAC

= 600 Ω; BAT = –24 V, R

LDC

= 300 Ω, R

LAC

= 600 Ω

Gain accuracy

0 dBm, 1 kHz

0°C to +70°C

–1

–2

–0.15

–0.10

—

+0.15

+0.10

0 dBm, 1 kHz

–40°C to +85°C

–1

–2

–0.20

–0.15

—

+0.20

+0.15

Variation with frequency

300 Hz to 3400 Hz

Relative to 1 kHz

0°C to +70°C

–1

–2

–0.15

–0.10

—

+0.15

+0.10

300 Hz to 3400 Hz

Relative to 1 kHz

–40°C to +85°C

–1

–2

–0.20

–0.15

—

+0.20

+0.15

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

LE7942B-1DJC

Mfr. #:

Buy LE7942B-1DJC

Manufacturer:

Microchip / Microsemi

Description:

Telecom Interface ICs 1CH, SLIC, P RV, PL32, RoHS

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LE7942B-1DJC

LE7942B-1DJC

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