ISL12008IB8Z Datasheet ISL12008IB8Z, ISL12008IB8Z-T | P10-P12

FN6690.1

September 26, 2008

Real Time Clock Registers

Addresses [00h to 06h, and 1Fh]

RTC REGISTERS (SC, MN, HR, DW, DT, MO, YR, SS)

These registers depict BCD representations of the time. As

such, SC (Seconds, address 00h) and MN (Minutes,

address 01h) range from 0 to 59, HR (Hour, address 02h) is

in 24-hour mode with a range from 0 to 23, DW (Day of the

Week, address 03h) is 1 to 7, DT (Date, address 04h) is 1 to

31, MO (Month, address 05h) is 1 to 12, YR (Year, address

06h) is 0 to 99, and SS (Sub-Seconds/Hundredths of

Seconds, address 1Fh) is 0 to 99. The default for all the time

keeping bits are set to “0” at power up.

Bit D7 of SC register contain the crystal enable/disable bit

(ST). Setting ST to “1” will disable the crystal from oscillating

and stop the counting in RTC register. When the ST bit is set

to “1”, it will casue the OF bit to set to “1” due to no crystal

oscillation on the X1 pin. The ST bit is set to “0” on power-up

for normal operation.

Bit D7 of MN register contain the Oscillator Fail Indicator bit

(OF). This bit is set to a “1” when the X1 pin has no

oscillation. This bit can be reset when the X1 has crystal

oscillation and a write to “0”. This bit can only be written as

“0” and not as a “1”. The OF bit is set to “1” at power-up from

a complete power down (V

and V

BAT

are removed).

Address 9, bit 7 is also used as the OF bit for DS1340

compatibility, and the two OF bits are interchangable.

Bits D6 and D7 of HR register (century/hours register)

contain the century enable bit (CEB) and the century bit

(CB). Setting CEB to a '1' will cause CB to toggle, either from

'0' to '1' or from '1' to '0' at the turn of the century (depending

upon its initial state). If CEB is set to a '0', CB will not toggle.

The DW register provides a Day of the Week status and uses

three bits DW2 to DW0 to represent the seven days of the

week. The counter advances in the cycle 1-2-3-4-5-6-7-1-2-

… The assignment of a numerical value to a specific day of

the week is arbitrary and may be decided by the system

software designer.

TABLE 1. REGISTER MEMORY MAP

ADDR. SECTION

REG

NAME

BIT REG

7 6 5 4 3 2 1 0

RTC

RANGE

DEFAULT

00h RTC SC ST SC22 SC21 SC20 SC13 SC12 SC11 SC10 0 to 59 00h

01h MN OF MN22 MN21 MN20 MN13 MN12 MN11 MN10 0 to 59 80h

02h HR CEB CB HR21 HR20 HR13 HR12 HR11 HR10 0 to 23 00h

03h DW00000DW12DW11DW101 to 700h

04h DT 0 0 DT21 DT20 DT13 DT12 DT11 DT10 1 to 31 00h

05h MO 0 0 0 MO20 MO13 MO12 MO11 MO10 1 to 12 00h

06h YR YR23 YR22 YR21 YR20 YR13 YR12 YR11 YR10 0 to 99 00h

07h Control DTR OUT FT DTR5 DTR4 DTR3 DTR2 DTR1 DTR0 N/A 80h

08h INT0ALMELPMODE00000N/A00h

09h OFOF0000000N/A80h

0Ah ATR BMATR1 BMATR0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 N/A 00h

0Bh Status SR ARST XSTOP RESEAL 0 0 ALM BAT RTCF N/A 03h

0Ch Alarm0 SCA ESCA ASC22 ASC21 ASC20 ASC13 ASC12 ASC11 ASC10 00 to 59 00h

0Dh MNA EMNA AMN22 AMN21 AMN20 AMN13 AMN12 AMN11 AMN10 00 to 59 00h

0Eh HRA EHRA 0 AHR21 AHR20 AHR13 AHR12 AHR11 AHR10 0 to 23 00h

0Fh DTA EDTA 0 ADT21 ADT20 ADT13 ADT12 ADT11 ADT10 1 to 31 00h

10h MOA EMOA 0 0 AMO20 AMO13 AMO12 AMO11 AMO10 1 to 12 00h

11h DWAEDWA0000ADW12ADW11ADW101 to 700h

1Fh

(Read-

Only)

RTC SS SS23 SS22 SS21 SS20 SS13 SS12 SS11 SS10 0 to 99 00h

NOTE: 0 = must be set to‘0’

ISL12008

FN6690.1

September 26, 2008

LEAP YEARS

Leap years add the day February 29 and are defined as those

years that are divisible by 4. Years divisible by 100 are not leap

years, unless they are also divisible by 400. This means that

the year 2000 is a leap year, the year 2100 is not. The

ISL12008 does not correct for the leap year in the year 2100.

Control and Status Registers

Addresses [07h to 0Bh]

The Control and Status Registers consist of the Status

Digital Trimming Registers.

Status Register (SR) [Address 0Bh]

The Status Register is located in the memory map at

address 0Bh. This is a volatile register that provides either

control or status of RTC failure, battery mode, alarm trigger,

crystal oscillator status, ReSeal™ and auto reset of status

bits.

REAL TIME CLOCK FAIL BIT (RTCF)

This bit is set to a “1” after a total power failure. This is a read

only bit that is set by hardware (ISL12008 internally) when

the device powers up after having lost all power to the device

(both V

and V

BAT

go to 0V). The bit is set regardless of

whether V

or V

BAT

is applied first. The loss of only one of

the supplies does not set the RTCF bit to “1”. On power-up

after a total power failure, all registers are set to their default

states and the clock will not increment until at least one byte

is written to the clock register. The first valid write to the RTC

section after a complete power failure resets the RTCF bit to

“0” (writing one byte is sufficient).

BATTERY BIT (BAT)

This bit is set to a “1” when the device enters battery backup

mode. This bit can be reset either manually by the user or

automatically reset by enabling the auto-reset bit (see ARST

bit). A write to this bit in the SR can only set it to “0”, not “1”.

ALARM BIT (ALM)

These bits announce if the alarm matches the real time

clock. If there is a match, the respective bit is set to “1”. This

bit can be manually reset to “0” by the user or automatically

reset by enabling the auto-reset bit (see ARST bit). A write to

this bit in the SR can only set it to “0”, not “1”.

NOTE: An alarm bit that is set by an alarm occurring during an SR

read operation will remain set after the read operation is complete.

ReSeal (RESEAL)

The ReSeal™ enables the device enter into the InterSeal™

Battery Saver mode after manufacture testing for board

functionality. The factory default setting of this bit is “0”. The

RESEAL must be set to “0” to enable the battery function

during normal operation or full functional testing. To use the

ReSeal function, simply set RESEAL bit to “1” after the

testing is completed. It will enable the InterSeal™ Battery

Saver mode and prevents battery current drain before it is

first used.

AUTO RESET ENABLE BIT (ARST)

This bit enables/disables the automatic reset of the BAT,

ALM and TMR status bits only. When ARST bit is set to “1”,

these status bits are reset to “0” after a valid read of the

respective status register (with a valid STOP condition).

When the ARST is cleared to “0”, the user must manually

reset the BAT and ALM bits.

Interrupt Control Register (INT) [Address 08h]

LOW POWER MODE BIT (LPMODE)

This bit enables/disables low power mode. With

LPMODE = “0”, the device will be in normal mode and the

BAT

supply will be used when V

< V

BAT

- V

BATHYS

and

< V

TRIP

. With LPMODE = “1”, the device will be in low

power mode and the V

BAT

supply will be used when

< V

BAT

-V

BATHYS

. There is a supply current saving of

about 600nA when using LPMODE = “1” with V

= 5V.

(See “Typical Performance Curves” on page 6: I

vs V

with LPMODE ON and OFF.)

ALARM ENABLE BIT (ALME)

This bit enables/disables the alarm function. When the ALME

bit is set to “1”, the alarm function is enabled. When the ALME

bit is cleared to “0”, the alarm function is disabled. ALME bit is

set to “0” at power-up.

Oscillator Fail Register (OF) [Address 09h]

OSCILLATOR FAIL BIT (OF)

This bit is set to a “1” when the X1 pin has no oscillation.

This bit can be reset when the X1 has crystal oscillation and

a write to “0”. This bit can only be written as “0” and not as a

“1”. The OF bit is set to “1” at power up from a complete

power down (V

and V

BAT

are removed). Address 1, bit 7

TABLE 2. STATUS REGISTER (SR)

ADDR 7 6 5 4 3 2 1 0

0Bh ARST 0 RESEAL 0 0 ALM BAT RTCF

Default 0 0 0 0 0 0 1 1

TABLE 3. INTERRUPT CONTROL REGISTER (INT)

ADDR7 6 5 4 3210

08h 0ALMELPMODE 0 0000

Default0 0 0 0 0000

TABLE 4. INTERRUPT CONTROL REGISTER (INT)

ADDR7 6543210

09h OF0000000

Default1 0000000

ISL12008

FN6690.1

September 26, 2008

is also used as the OF bit for M41T00S compatibility, and the

two OF bits are interchangable.

Analog Trimming Register (ATR) [Address 0Ah]

ANALOG TRIMMING REGISTER (ATR<5:0>)

Six analog trimming bits, ATR0 to ATR5, are provided in

order to adjust the on-chip load capacitance value for

frequency compensation of the RTC. Each bit has a different

weight for capacitance adjustment. For example, using a

Citizen CFS-206 crystal with different ATR bit combinations

provides an estimated ppm adjustment range from -34ppm

to +80ppm to the nominal frequency compensation. The

combination of analog and digital trimming can give up to

-97.0695ppm to +206.139ppm of total adjustment.

The effective on-chip series load capacitance, C

LOAD

ranges from 9pF to 40.5pF with a mid-scale value of 12.5pF

(default). C

LOAD

is changed via two digitally controlled

capacitors, C

and C

, connected from the X1 and X2

pins to ground (see Figure 9). The value of C

and C

are

given in Equation 1:

The effective series load capacitance is the combination of

and C

in Equation 2:

where b5 is ATR5 bit, b4 is ATR4 bit, b3 is ATR3 bit, b2 is

ATR1 bit, and b0 is ATR0 bit.

For example, C

LOAD

(ATR = 000000b [0d]) = 12.5pF, C

LOAD

(ATR = 100000b [32d]) = 4.5pF and C

LOAD

(ATR = 011111b

[31d]) = 20.25pF. The entire range for the series combination

of load capacitance goes from 4.5pF to 20.25pF in 0.25pF

steps. Note that these are typical values.

BATTERY MODE ATR SELECTION (BMATR <1:0>)

Since the accuracy of the crystal oscillator is dependent on

the V

BAT

operation, the ISL12008 provides the

capability to adjust the capacitance between V

and V

BAT

when the device switches between power sources.

Digital Trimming Register (DTR) [Address 07h]

DIGITAL TRIMMING REGISTER (DTR<5:0>)

Six digital trimming bits, DTR0 to DTR5, are provided to

adjust the average number of counts per second and

average the ppm error to achieve better accuracy.

• DTR5 is a sign bit. DTR5 = “0” means frequency

compensation is < 0. DTR5 = “1” means frequency

compensation is > 0.

• DTR<4:0> are scale bits. With DTR5 = “0”, DTR<4:0>

gives -2.0345ppm adjustment per step. With DTR5 = “1”,

DTR<4:0> gives +4.0690ppm adjustment per step.

A range from -63.0696ppm to +126.139ppm can be

represented by using these 3 bits.

For example, with DTR = 11111, the digital adjustment is

(1111b[15d]*4.0690) = +126.139ppm. With DTR = 01111, the

digital adjustment is (-(1111b[15d]*2.0345)) = -63.0696ppm.

512HZ FREQUENCY OUTPUT ENABLE BIT (FT)

This bit enables/disables the 512Hz frequency output on the

FT/OUT pin. When the FT is set to “1”, the FT/OUT pin

outputs the 512Hz frequency, regardless of the Digital Output

selection bit (OUT). The 512Hz frequency output is used for

crystal compensation with ATR and DTR registers. When the

FT is set to “0”, the 512Hz frequency is disabled and the

function of FT/OUT pin is selected by the Digital Output

selection bit (OUT). The FT bit is set to “0” on power-up. The

FT/OUT pin is an open drain output requires the use of a

pull-up resistor.

TABLE 5. ANALOG TRIMMING REGISTER (ATR)

ADDR7 6 543210

0Ah BMATR1 BMATR0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0

Default0 0 000000

FIGURE 9. DIAGRAM OF ATR

CRYSTAL

OSCILLATOR

16 b5⋅ 8 b4 4 b3 2 b2 1 b1 0.5 b0 9+⋅+⋅+⋅+⋅+⋅+()pF=

(EQ. 1)

LOAD

-----------

⎝⎠

⎛⎞

-----------------------------------

LOAD

16 b5

⋅ 8 b4 4 b3 2 b2 1 b1 0.5 b09+⋅+⋅+⋅+⋅+⋅+

------------------------------------------------------------------------------------------------------------------------------

⎝⎠

⎛⎞

(EQ. 2)

BMATR1 BMATR0

DELTA

CAPACITANCE

BAT

TO C

VDD

)

0 0 0pF

0 1 -0.5pF (≈ +2ppm)

1 0 +0.5pF (≈ -2ppm)

1 1 +1pF (≈ -4ppm)

TABLE 6. DIGITAL TRIMMING REGISTER (DTR)

ADDR 7 6 543210

07h OUT FT DTR5 DTR4 DTR3 DTR2 DTR1 DTR0

Default0 0 000000

ISL12008

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

ISL12008IB8Z

Mfr. #:

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Manufacturer:

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Description:

Real Time Clock LW PWR RTC W/RESEAL 8LD

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