4
FN6690.1
September 26, 2008
f
SCL
SCL Frequency 400 kHz
t
IN
Pulse width Suppression Time at SDA and
SCL Inputs
Any pulse narrower than the max
spec is suppressed.
50 ns
t
AA
SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of
V
DD
, until SDA exits the 30% to
70% of V
DD
window.
900 ns
t
BUF
Time the Bus Must be Free Before the Start
of a New Transmission
SDA crossing 70% of V
DD
during
a STOP condition, to SDA
crossing 70% of V
DD
during the
following START condition.
1300 ns
t
LOW
Clock LOW Time Measured at the 30% of V
DD
crossing.
1300 ns
t
HIGH
Clock HIGH Time Measured at the 70% of V
DD
crossing.
600 ns
t
SU:STA
START Condition Setup Time SCL rising edge to SDA falling
edge. Both crossing 70% of V
DD
.
600 ns
t
HD:STA
START Condition Hold Time From SDA falling edge crossing
30% of V
DD
to SCL falling edge
crossing 70% of V
DD
.
600 ns
t
SU:DAT
Input Data Setup Time From SDA exiting the 30% to 70%
of V
DD
window, to SCL rising edge
crossing 30% of V
DD.
100 ns
t
HD:DAT
Input Data Hold Time From SCL falling edge crossing
30% of V
DD
to SDA entering the
30% to 70% of V
DD
window.
20 900 ns
t
SU:STO
STOP Condition Setup Time From SCL rising edge crossing
70% of V
DD
, to SDA rising edge
crossing 30% of V
DD
.
600 ns
t
HD:STO
STOP Condition Hold Time From SDA rising edge to SCL
falling edge. Both crossing 70% of
V
DD
.
600 ns
t
DH
Output Data Hold Time From SCL falling edge crossing
30% of V
DD
, until SDA enters the
30% to 70% of V
DD
window.
0ns
t
R
SDA and SCL Rise Time From 30% to 70% of V
DD
20 +
0.1 x Cb
300 ns 6, 7
t
F
SDA and SCL Fall Time From 70% to 30% of V
DD
20 +
0.1 x Cb
300 ns 6, 7
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF 6, 7
Rpu SDA and SCL Bus Pull-Up Resistor Off-Chip Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about
2kΩ to~2.5kΩ.
For Cb = 40pF, max is about 15kΩ
to ~20kΩ.
1kΩ 6, 7
NOTES:
2. FT/OUT inactive.
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the V
DD SR-
specification must be followed.
5. Typical values are for T = +25°C and 3.3V supply voltage.
6. Limits should be considered typical and are not production tested.
7. These are I
2
C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
Serial Interface Specifications Recommended Operating Conditions. Unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 8)
TYP
(Note 5)
MAX
(Note 8) UNITS NOTES
ISL12008
5
FN6690.1
September 26, 2008
SDA vs SCL Timing
Symbol Table
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t
F
t
LOW
t
BUF
t
AA
t
R
WAVEFORM INPUTS OUTPUTS
Must be steady Will be steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Changing:
State Not Known
N/A Center Line is
High Impedance
ISL12008
6
FN6690.1
September 26, 2008
General Description
The ISL12008 device is a low power real time clock with
timing and crystal compensation, clock/calendar, power fail
indicator, software alarm, and intelligent battery backup
switching.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, seconds, and sub-seconds. The device has
calendar registers for date, month, year and day of the week.
The calendar is accurate through 2099, with automatic leap
year correction.
The ISL12008's powerful alarm can be set to any
clock/calendar value for a match. For example, every
minute, every Tuesday or at 5:23 AM on March 21. The
alarm status is available by checking the Status Register.
The device also offers a backup power input pin. This V
BAT
pin allows the device to be backed up by battery or super
capacitor with automatic switchover from V
DD
to V
BAT
. The
entire ISL12008 device is fully operational from 2.7V to 5.5V
and the clock/calendar portion of the device remains fully
operational down to 1.8V in battery mode.
Pin Descriptions
X1, X2
The X1 and X2 pins are the input and output, respectively, of
an inverting amplifier. An external 32.768kHz quartz crystal is
used with the ISL12008 to supply a timebase for the real time
clock. Internal compensation circuitry provides high accuracy
over the operating temperature range from -40°C to +85°C.
This oscillator compensation network can be used to calibrate
Typical Performance Curves Temperature is +25°C, unless otherwise specified.
FIGURE 1. I
BAT
vs V
BAT
FIGURE 2. I
BAT
vs TEMPERATURE AT V
BAT
= 3V
FIGURE 3. I
DD1
vs TEMPERATURE
FIGURE 4. I
DD1
vs V
DD
WITH LPMODE ON AND OFF
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.2
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
V
BAT
(V)
I
BAT
(µA)
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
-40-200 20406080
TEMPERATURE (°C)
I
BAT
(µA)
1.0
1.5
2.0
2.5
3.0
3.5
-40-200 20406080
TEMPERATURE (°C)
I
DD
(µA)
V
DD
= 3.3V
V
DD
= 5V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.82.32.83.33.84.34.85.3
V
DD
(V)
I
CC
(µA)
LP MODE OFF
LP MODE ON
FIGURE 5. STANDARD OUTPUT LOAD FOR TESTING THE
DEVICE WITH V
DD
= 5.0V
SDA
AND
FT/OUT
1533Ω
100pF
5.0V
FOR V
OL
= 0.4V
AND I
OL
= 3mA
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V
DD
= 5V
ISL12008

ISL12008IB8Z

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Real Time Clock LW PWR RTC W/RESEAL 8LD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet