16
FN6690.1
September 26, 2008
Application Section
Oscillator Crystal Requirements
The ISL12008 uses a standard 32.768kHz crystal. Either
through hole or surface mount crystals can be used. Table 7
lists some recommended surface mount crystals and the
parameters of each. This list is not exhaustive and other
surface mount devices can be used with the ISL12008 if
their specifications are very similar to the devices listed.
The crystal should have a required parallel load capacitance
of 12.5pF and an equivalent series resistance of less than
50k. The crystal’s temperature range specification should
match the application. Many crystals are rated for -10°C to
+60°C (especially through-hole and tuning fork types), so an
appropriate crystal should be selected if extended
temperature range is required.
Crystal Oscillator Frequency Adjustment
The ISL12008 device contains circuitry for adjusting the
frequency of the crystal oscillator. This circuitry can be used
to trim oscillator initial accuracy as well as adjust the
frequency to compensate for temperature changes.
The Analog Trimming Register (ATR) is used to adjust the
load capacitance seen by the crystal. There are 6 bits of ATR
control, with linear capacitance increments available for
adjustment. Since the ATR adjustment is essentially “pulling”
the frequency of the oscillator, the resulting frequency
changes will not be linear with incremental capacitance
changes. The equations (which govern pulling) show that
lower capacitor values of ATR adjustment will provide larger
increments. Also, the higher values of ATR adjustment will
produce smaller incremental frequency changes. The range
afforded by the ATR adjustment with a typical surface mount
crystal is typically -34ppm to +80ppm around the ATR = 0
default setting because of this property. The user should note
this when using the ATR for calibration. The temperature drift
of the capacitance used in the ATR control is extremely low,
so this feature can be used for temperature compensation
with good accuracy.
In addition to the analog compensation afforded by the
adjustable load capacitance, a digital compensation feature
is available for the ISL12008. There are 6 bits known as the
Digital Trimming Register (DTR). The range provided is
-63.0695ppm to +126.139ppm. DTR operates by adding or
skipping pulses in the clock counter. It is very useful for
coarse adjustments of frequency drift over temperature or
extending the adjustment range available with the ATR
register.
Initial accuracy is best adjusted by enabling the 512Hz
frequency output (using the FT bit, address 08h bit 6), and
monitoring the FT/OUT pin with a calibrated frequency
counter. The gating time should be set long enough to
ensure accuracy to at least 1ppm. To calculate the ppm on
the measured 512Hz, simply divide the measured 512Hz by
512, then subtract 1 from the result and mulitple by
1,000,000. Please see Equation 3 for the formula:
The ATR should be set to the center position, or 00000b, to
begin with. Once the initial measurement is made, then the
ATR register can be changed to adjust the frequency. Note
for a range of 0 to 31 for the ATR register will increased
capacitance and lower the frequency with 31 for the
maximum negative correction, and for a range of 32 to 63 for
the ATR register will decreased capacitance and increase
the frequency with 32 for the maximum positive correction. If
the initial measurement shows the frequency is far off, it will
be necessary to use the DTR register to do a coarse
adjustment. Note that most all crystals will have tight enough
initial accuracy at room temperature so that a small ATR
register adjustment should be all that is needed.
Temperature Compensation
The ATR and DTR controls can be combined to provide
crystal drift temperature compensation. The typical
32.768kHz crystal has a drift characteristic that is similar to
that shown in Figure 15. There is a turnover temperature
(T
0
) where the drift is very near zero. The shape is parabolic
as it varies with the square of the difference between the
actual temperature and the turnover temperature.
TABLE 7. SUGGESTED SURFACE MOUNT CRYSTALS
MANUFACTURER PART NUMBER
Citizen CM200S
Epson MC-405, MC-406
Raltron RSM-200S
SaRonix 32S12
Ecliptek ECPSM29T-32.768K
ECS ECX-306
Fox FSM-327
ppm = (FT/512 - 1)*1E6
(EQ. 3)
TEMPERATURE (°C)
-160
-140
-120
-100
-80
-60
-40
-20
0
-40-30-20-100 1020304050607080
PPM
FIGURE 15. RTC CRYSTAL TEMPERATURE DRIFT
ISL12008
17
FN6690.1
September 26, 2008
If full industrial temperature compensation is desired in an
ISL12008 circuit, then both the DTR and ATR registers will
need to be utilized (total correction range = -97.0695ppm to
+206.139ppm).
A system to implement temperature compensation would
consist of the ISL12008, a temperature sensor, and a
microcontroller. These devices may already be in the system
so the function will just be a matter of implementing software
and performing some calculations. Fairly accurate
temperature compensation can be implemented just by
using the crystal manufacturer’s specifications for the
turnover temperature T
0
and the drift coefficient (β). The
formula for calculating the oscillator adjustment necessary is
Equation 4:
Once the temperature curve for a crystal is established, then
the designer should decide at what discrete temperatures
the compensation will change. Since drift is higher at
extreme temperatures, the compensation may not be
needed until the temperature is greater than +20°C from T
0
.
A sample curve of the ATR setting vs Frequency Adjustment
for the ISL12008 and a typical RTC crystal is given in
Figure 16. This curve may vary with different crystals, so it is
good practice to evaluate a given crystal in an ISL12008
circuit before establishing the adjustment values.
This curve is then used to figure what ATR and DTR settings
are used for compensation. The results would be placed in a
lookup table for the microcontroller to access.
Layout Considerations
The crystal input at X1 has a very high impedance, and
oscillator circuits operating at low frequencies (such as
32.768kHz) are known to pick up noise very easily if layout
precautions are not followed. Most instances of erratic
clocking or large accuracy errors can be traced to the
susceptibility of the oscillator circuit to interference from
adjacent high speed clock or data lines. Careful layout of the
RTC circuit will avoid noise pickup and insure accurate
clocking.
Figure 17 shows a suggested layout for the ISL12008 device
using a surface mount crystal. Two main precautions should
be followed:
1. Do not run the serial bus lines or any high speed logic
lines in the vicinity of the crystal. These logic level lines
can induce noise in the oscillator circuit to cause
misclocking.
2. Add a ground trace around the crystal with one end
terminated at the chip ground. This will provide
termination for emitted noise in the vicinity of the RTC
device.
In addition, it is a good idea to avoid a ground plane under
the X1 and X2 pins and the crystal, as this will affect the load
capacitance and therefore the oscillator accuracy of the
circuit. If the FT/OUT pin is used as a clock, it should be
routed away from the RTC device as well. The traces for the
V
BAT
and V
CC
pins can be treated as a ground, and should
be routed around the crystal.
Super Capacitor Backup
The ISL12008 device provides a VBAT pin which is used for
a battery backup input. A super capacitor can be used as an
alternative to a battery in cases where shorter backup times
are required. Since the battery backup supply current
required by the ISL12008 is extremely low, it is possible to
get months of backup operation using a super capacitor.
Typical capacitor values are a few µF to 1F or more,
depending on the application.
If backup is only needed for a few minutes, then a small
inexpensive electrolytic capacitor can be used. For extended
periods, a low leakage, high capacity super capacitor is the
best choice. These devices are available from such vendors
as Panasonic and Murata. The main specifications include
working voltage and leakage current. If the application is for
charging the capacitor from a +5V ±5% supply with a signal
diode, then the voltage on the capacitor can vary from ~4.5V
to slightly over 5.0V. A capacitor with a rated WV of 5.0V
may have a reduced lifetime if the supply voltage is slightly
high. The leakage current should be as small as possible.
For example, a super capacitor should be specified with
leakage of well below 1µA. A standard electrolytic capacitor
with DC leakage current in the microamps will have a
severely shortened backup time.
Adjustment(ppm) T T
0
()
2
=
β
(EQ. 4)
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
0 5 10 15 20 25 30 35 40 45 50 55 60
ATR SETTING
PPM ADJUSTMENT
FIGURE 16. ATR SETTING vs OSCILLATOR FREQUENCY
ADJUSTMENT
FIGURE 17. SUGGESTED LAYOUT FOR ISL12008 AND
CRYSTAL
ISL12008
18
FN6690.1
September 26, 2008
Following are some examples with equations to assist with
calculating backup times and required capacitance for the
ISL12008 device. The backup supply current plays a major
part in these equations, and a typical value was chosen for
example purposes. For a robust design, a margin of 30%
should be included to cover supply current and capacitance
tolerances over the results of the calculations. Even more
margin should be included if periods of very warm
temperature operation are expected.
EXAMPLE 1: CALCULATING BACKUP TIME GIVEN
VOLTAGES AND CAPACITOR VALUE
In Figure 18, use C
BAT
= 0.47F and V
CC
= 5V. With V
CC
= 5V,
the voltage at V
BAT
will approach 4.7V as the diode turns off
completely. The ISL12008 is specified to operate down to
V
BAT
= 1.8V. The capacitance charge/discharge in Equation 5
is used to estimate the total backup time as follows:
Rearranging gives Equation 6:
C
BAT
is the backup capacitance and dV is the change in
voltage from fully charged to loss of operation. Note that
I
TOT
is the total of the supply current of the ISL12008 (I
BAT
)
plus the leakage current of the capacitor and the diode, I
LKG
.
In these calculations, I
LKG
is assumed to be extremely small
and will be ignored. If an application requires extended
operation at temperatures over +50°C, these leakages will
increase and hence reduce backup time.
Note that I
BAT
changes with V
BAT
almost linearly (see
“Typical Performance Curves” on page 6). This allows us to
make an approximation of I
BAT
, using a value midway
between the two endpoints. The typical linear equation for
I
BAT
vs V
BAT
is shown in Equation 7:
Using Equation 7 to solve for the average current given 2
voltage points gives Equation 8:
Combining with Equation 6 gives the equation for backup
time in Equation 9:
where:
C
BAT
= 0.47F
V
BAT2
= 4.7V
V
BAT1
= 1.8V
I
LKG
= 0 (assumed minimal)
Solving Equation 8 for this example (I
BATAVG
= 4.387E-7A)
yields Equation 10:
Since there are 86,400 seconds in a day, this corresponds to
35.96 days. If the 30% tolerance is included for capacitor
and supply current tolerances, then worst case backup time
would be represented in Equation 11:
EXAMPLE 2: CALCULATING A CAPACITOR VALUE FOR
A GIVEN BACKUP TIME
Referring to Figure 18 again, the capacitor value needs to be
calculated to give 2 months (60 days) of backup time, given
V
CC
= 5.0V. As in Example 1, the V
BAT
voltage will vary from
4.7V down to 1.8V. We will need to rearrange Equation 6 to
solve for capacitance in Equation 12:
Using the terms previously described, Equation 12 becomes
Equation 13:
where:
t
BACKUP
= 60 days*86,400 sec/day = 5.18 E6 seconds
I
BATAVG
= 4.387 E-7A (same as Example 1)
I
LKG
= 0 (assumed)
V
BAT2
= 4.7V
V
BAT1
= 1.8VSolving gives
C
BAT
= 5.18 E6*(4.387 E-7)/(2.9) = 0.784F
If the 30% tolerance is included for tolerances, then worst
case capacitor value would be:
FIGURE 18. SUPERCAPACITOR CHARGING CIRCUIT
2.7V TO 5.5V
V
CC
V
BAT
GND
1N4148
C
BAT
I = C
BAT
*dV/dT
(EQ. 5)
dT = C
BAT
*dV/I
TOT
to solve for backup time.
(EQ. 6)
I
BAT
= 1.031E-7*(V
BAT
) + 1.036E-7A
(EQ. 7)
I
BATAVG
= 5.155E-8*(V
BAT2
+ V
BAT1
) + 1.036E-7A
(EQ. 8)
t
BACKUP
= C
BAT
*(V
BAT2
- V
BAT1
) / (I
BATAVG
+ I
LKG
)
(EQ. 9)
seconds
(EQ. 10)t
BACKUP
0.47 2.9()4.38E 7 3.107E6s==
(EQ. 11)
C
BAT
0.70 35.96 25.2= days=
C
BAT
= dT*I/dV
(EQ. 12)
C
BAT
= t
BACKUP
*(I
BATAVG
+ I
LKG
)/(V
BAT2
– V
BAT1
)
(EQ. 13)
(EQ. 14)C
BAT
1.3 0.784 1.02F==
ISL12008

ISL12008IB8Z

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Real Time Clock LW PWR RTC W/RESEAL 8LD
Lifecycle:
New from this manufacturer.
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