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M93C56-MN6P

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
DC and AC parameters M93C46, M93C56, M93C66, M93C76, M93C86
22/34 Doc ID 4997 Rev 12
Table 18. DC characteristics (M93Cx6-W, device grade 3)
Symbol Parameter Test condition Min.
(1)
1. New product: identified by Process Identification letter W or G or S.
Max.
(1)
Unit
I
LI
Input leakage current 0V ≤ V
IN
≤ V
CC
±2.5 µA
I
LO
Output leakage current 0V ≤ V
OUT
≤ V
CC
, Q in Hi-Z ±2.5 µA
I
CC
Supply current (CMOS
inputs)
V
CC
= 5 V, S = V
IH
, f = 2 MHz,
Q = open
2 mA
V
CC
= 2.5 V, S = V
IH
, f = 2 MHz,
Q = open
1 mA
I
CC1
Supply current (Standby)
V
CC
= 2.5 V, S = V
SS
, C = V
SS
,
ORG = V
SS
or V
CC
,
pin7 = V
CC
, V
SS
or Hi-Z
5 µA
V
IL
Input low voltage (D, C,
S)
–0.45 0.2 V
CC
V
V
IH
Input high voltage (D, C,
S)
0.7 V
CC
V
CC
+ 1 V
V
OL
Output low voltage (Q)
V
CC
= 5 V, I
OL
= 2.1 mA 0.4 V
V
CC
= 2.5 V, I
OL
= 100 µA 0.2 V
V
OH
Output high voltage (Q)
V
CC
= 5 V, I
OH
= –400 µA 0.8 V
CC
V
V
CC
= 2.5 V, I
OH
= –100 µA V
CC
–0.2 V
Table 19. DC characteristics (M93Cx6-R)
Symbol Parameter Test condition Min.
(1)
1. This product is under development. For more information, please contact your nearest ST sales office.
Max.
(1)
Unit
I
LI
Input leakage current 0V ≤ V
IN
≤ V
CC
±2.5 µA
I
LO
Output leakage current 0V ≤ V
OUT
≤ V
CC
, Q in Hi-Z ±2.5 µA
I
CC
Supply current (CMOS
inputs)
V
CC
= 5 V, S = V
IH
, f = 2 MHz,
Q = open
2 mA
V
CC
= 1.8 V, S = V
IH
, f = 1 MHz,
Q = open
1 mA
I
CC1
Supply current (Standby)
V
CC
= 1.8 V, S = V
SS
, C = V
SS
,
ORG = V
SS
or V
CC
,
pin7 = V
CC
, V
SS
or Hi-Z
2 µA
V
IL
Input low voltage (D, C,
S)
–0.45 0.2 V
CC
V
V
IH
Input high voltage (D, C,
S)
0.8 V
CC
V
CC
+ 1 V
V
OL
Output low voltage (Q) V
CC
= 1.8 V, I
OL
= 100 µA 0.2 V
V
OH
Output high voltage (Q) V
CC
= 1.8 V, I
OH
= –100 µA V
CC
–0.2 V
M93C46, M93C56, M93C66, M93C76, M93C86 DC and AC parameters
Doc ID 4997 Rev 12 23/34
Table 20. AC characteristics (M93Cx6, device grade 6 or 3)
Test conditions specified in Table 12 and Table 9
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SK
Clock frequency D.C. 2 MHz
t
SLCH
Chip Select low to Clock high 50 ns
t
SHCH
t
CSS
Chip Select setup time
M93C46, M93C56, M93C66
50 ns
Chip Select setup time
M93C76, M93C86
50 ns
t
SLSH
(1)
1. Chip Select Input (S) must be brought low for a minimum of t
SLSH
between consecutive instruction cycles.
t
CS
Chip Select low to Chip Select high 200 ns
t
CHCL
(2)
2. t
CHCL
+ t
CLCH
≥ 1 / f
C
.
t
SKH
Clock high time 200 ns
t
CLCH
(2)
t
SKL
Clock low time 200 ns
t
DVCH
t
DIS
Data in setup time 50 ns
t
CHDX
t
DIH
Data in hold time 50 ns
t
CLSH
t
SKS
Clock setup time (relative to S) 50 ns
t
CLSL
t
CSH
Chip Select hold time 0 ns
t
SHQV
t
SV
Chip Select to READY/BUSY status 200 ns
t
SLQZ
t
DF
Chip Select low to output Hi-Z 100 ns
t
CHQL
t
PD0
Delay to output low 200 ns
t
CHQV
t
PD1
Delay to output valid 200 ns
t
W
t
WP
Erase or Write cycle time 5 ms
Table 21. AC characteristics (M93Cx6-W, device grade 6)
Test conditions specified in Table 13 and Table 10
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SK
Clock frequency D.C. 2 MHz
t
SLCH
Chip Select low to Clock high 50 ns
t
SHCH
t
CSS
Chip Select setup time 50 ns
t
SLSH
(1)
t
CS
Chip Select low to Chip Select high 200 ns
t
CHCL
(2)
t
SKH
Clock high time 200 ns
t
CLCH
(2)
t
SKL
Clock low time 200 ns
t
DVCH
t
DIS
Data in setup time 50 ns
t
CHDX
t
DIH
Data in hold time 50 ns
t
CLSH
t
SKS
Clock setup time (relative to S) 50 ns
t
CLSL
t
CSH
Chip Select hold time 0 ns
t
SHQV
t
SV
Chip Select to READY/BUSY status 200 ns
DC and AC parameters M93C46, M93C56, M93C66, M93C76, M93C86
24/34 Doc ID 4997 Rev 12
t
SLQZ
t
DF
Chip Select low to output Hi-Z 100 ns
t
CHQL
t
PD0
Delay to output low 200 ns
t
CHQV
t
PD1
Delay to output valid 200 ns
t
W
t
WP
Erase or Write cycle time 5 ms
1. Chip Select Input (S) must be brought low for a minimum of t
SLSH
between consecutive instruction cycles.
2. t
CHCL
+ t
CLCH
≥ 1 / f
C
.
Table 22. AC characteristics (M93Cx6-W, device grade 3)
Test conditions specified in Table 13 and Table 10
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SK
Clock frequency D.C. 2 MHz
t
SLCH
Chip Select low to Clock high 50 ns
t
SHCH
t
CSS
Chip Select set-up time 50 ns
t
SLSH
(1)
1. Chip Select Input (S) must be brought low for a minimum of t
SLSH
between consecutive instruction cycles.
t
CS
Chip Select low to Chip Select high 200 ns
t
CHCL
(2)
2. t
CHCL
+ t
CLCH
≥ 1 / f
C
.
t
SKH
Clock high time 200 ns
t
CLCH
(2)
t
SKL
Clock low time 200 ns
t
DVCH
t
DIS
Data in set-up time 50 ns
t
CHDX
t
DIH
Data in hold time 50 ns
t
CLSH
t
SKS
Clock set-up time (relative to S) 50 ns
t
CLSL
t
CSH
Chip Select hold time 0 ns
t
SHQV
t
SV
Chip Select to READY/BUSY status 200 ns
t
SLQZ
t
DF
Chip Select low to output Hi-Z 100 ns
t
CHQL
t
PD0
Delay to output low 200 ns
t
CHQV
t
PD1
Delay to output valid 200 ns
t
W
t
WP
Erase or Write cycle time 5 ms
Table 21. AC characteristics (M93Cx6-W, device grade 6) (continued)
Test conditions specified in Table 13 and Table 10
Symbol Alt. Parameter Min. Max. Unit
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M93C56-MN6P

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Manufacturer:
STMicroelectronics
Description:
IC EEPROM 2K SPI 2MHZ 8SO
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