DS2731
Cache-Memory Battery-Backup Management IC
4 _______________________________________________________________________________________
BUCK REGULATOR AND POWER MUX CIRCUIT ELECTRICAL CHARACTERISTICS
(V
IN
= +10.8V to +13.2V, T
A
= -20°C to +70°C, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Auxiliary Input Trip Threshold V
TRIP
(Note 1) 2.85 2.93 3.00 V
Auxiliary Input Trip Hysteresis V
HYS-TRIP
Relative to actual V
TRIP
50 80 150 mV
Multiplexer Delay
Break-Before-Make
t
BREAK
Switching to/from BATT+
(Note 11)
1 µs
Power Multiplexer On-Resistance R
MUX
I
MUX
= 10mA, BATT+ or AUX source 0.6 1.0
Regulator Output Voltage Range V
REG
Set by V
DIV
pin voltage 0.9 2.5 V
DIV Pin Voltage Range V
DIV
0.4 V
REF
V
Regulator Output Voltage Error V
ERR-REG
(Note 9) -5.0 +5.0 %
Low-Battery Threshold
Adjustment Range
V
SLEEP
2.75 3.00 V
LO_BATT Pin Voltage Range V
LO-BATT
0.6 V
REF
V
V
REF
Voltage V
REF
1.220 1.238 1.260 V
1.22 126.00 µA
V
REF
Load Range
(Equivalent Resistance)
I
REF
1000 10 k
Buck Regulator Switching Period t
SW-REG
50mA (Note 9) 500 ns
Regulator Undervoltage Lockout V
UVLO-REG
2.45 2.70 V
Switching Power
pFET Resistance
R
DSON-SP
I
OUT
= 100mADC
BATT+ = 3.0V, V
AUX
= 0 (Note 10)
0.6
Switching Power
nFET Resistance
R
DSON-SN
I
OUT
= 100mADC
BATT+ = 3.0V, V
AUX
= 0 (Note 10)
1.2
nFET Off Threshold I
OFFN
0 40 80 mA
Switching Power
pFET Overcurrent Limit
I
OCLP
500 750 1000 mA
Switching Power
nFET Overcurrent Limit
I
OCLN
400 650 900 mA
VREG Pin Leakage I
LKG-R EG
-2 +2 µA
DS2731
Cache-Memory Battery-Backup Management IC
_______________________________________________________________________________________ 5
THERMAL PROTECTION CHARACTERISTICS
(V
IN
= +10.8V to +13.2V, T
A
= -20°C to +70°C, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
THM Pin Internal Pullup Voltage V
THM
(Notes 1, 12) V
CBIAS
V
THM Pin Internal Resistance R
THM
THM to C
BIAS
(Note 12) 9.8 10.0 10.2 k
Thermistor Overtemperature
HALT Threshold
V
HOT
(Notes 12, 13) 0.271 0.283 0.292
Ratio to
V
CBIAS
Thermistor Overtemperature
Resume Threshold
V
HYS-HOT
(Notes 12, 13) 0.3055
Ratio to
V
CBIAS
Thermistor Undertemperature
HALT Threshold
V
COLD
(Notes 12, 13) 0.727 0.739 0.748
Ratio to
V
CBIAS
Thermistor Undertemperature
Resume Threshold
V
HYS-COLD
(Notes 12, 13) 0.714
Ratio to
V
CBIAS
Thermistor Disable
Threshold
V
DISABLE
(Notes 12, 13) 0.02 0.03 0.04
Ratio to
V
CBIAS
Internal Overtemperature
Protection Threshold CCCV
T
PROTECT_CCCV
(Note 12) 160 °C
Internal Overtemperature
Hysteresis CCCV
T
HYS-PROTECT_CCCV
(Note 12) -20 °C
Internal Overtemperature
Protection Threshold MEM_REG
T
PROTECT_MEMREG
(Note 14) 165 °C
Internal Overtemperature
Hysteresis MEM_REG
T
HYS-PROTECT_
MEMREG
(Note 14) -15 °C
Charging Current Reduction
Threshold
T
CHOKE
(Note 12) 100 °C
Charging Current Reduction Rate T
CHOKE_RATE
(Note 12) 133 mA/°C
Note 1: All voltages referenced to AGND pin.
Note 2: V
CIN
is equivalent to V
AUX
when V
AUX
is greater than V
TRIP
, otherwise V
CIN
is equivalent to V
BATT+
.
Note 3: Supply-current specification is only for current drain of the IC and does not include cell-charge current, load-supply cur-
rent, or any external resistor bias currents. The only exception is I
SLEEP
, which does account for complete current drain of
the lithium cell during low-battery conditions.
Note 4: Below this voltage, the input is guaranteed to be logic-low.
Note 5: Operating from 3.3V ±10%.
Note 6: Above this voltage, the input is guaranteed to be logic-high.
Note 7: Assumes an R
SNS
value of 0.05.
Note 8: Relative to V
CV
.
Note 9: With recommended application circuit.
Note 10: Includes complete package resistance.
Note 11: This specification is from the rising or falling edge of ENS to the closure of the switch and includes whatever delay is in the
internal logic and FET drivers.
Note 12: Applies to charger.
Note 13: Multiply these values by C
BIAS
voltage to get value in volts. Recommended value of resistor in divider network is 10k ±1%.
Tolerance includes tolerances of internal resistance and C
BIAS
voltage.
Note 14: Applies to memory buck regulator.
DS2731
Cache-Memory Battery-Backup Management IC
6 _______________________________________________________________________________________
DS2731
U1
22
CHG1
21 CHG
L2
6.8µH
CHG2
25 SNS
SNS
10
AGND
3
CTG
C1
10µF
R9
0.050
R5
360k
R4
240k
R3
590k
18CHARGECLED
Y
CHARGE
R8
4.7k
17FAULTFLED
R
FAULT
R7
4.7k
16DONEDLED
G
DONE
R6
4.7k
23VIN
VIN
24CGATECGND
CGATE
THMI
10k OR 103AT-2
C7
10µF
C5
22µF
C4
22µF
J3
VIN
C6
47µF
1
J1
BATTERY+
1
J2
BATTERY-
J9
TEST
1
J8
MEM+
1
J10
MEM-
1
1
4AUX
AUX
15ENCENC-RES
ENC
14ENSENS-RES
ENS
5CBIAS
CBIAS
12LO_BATT
LO_BATT
13DIV
DIV
11REF
REF
J5
AUX+
1
J6
ENC
J7
ENS
1
1
J4
CGND
1
R2
10.2k
R13
2.49k
R1
56.2k
1MARGIN
MARGIN
2STMR
STMR
27RSET
RSET
20
CGND1
19 CGND
CGND2
28 THM
THM
26 BATT+
BATT+
ISOLATED GROUND AREA
ISOLATED GROUND AREA
6
VREG
8LX
VREG
L1
2.2µH
LX
7 CIN
CIN
9
SGND
C2
47µF
C3
47µF
C
S
C
SYSTEM
CONTROL
SYSTEM CONTROL
Figure 1. Typical Application Diagram

DS2731E+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Battery Management Cache-Memory Battery-Backup
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet