IDT
TM
56-pin CK505 for Embedded Intel Systems 1614B—01/21/10
ICS9EPRS525
10
56-pin CK505 for Embedded Systems
FS
L
C
2
B0b7
FS
L
B
1
B0b6
FS
L
A
1
B0b5
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
0 0 0 266.66
0 0 1 133.33
0 1 0 200.00
0 1 1 166.66
1 0 0 333.33
1 0 1 100.00
1 1 0 400.00
111
1. FS
L
A and FS
L
B are low-threshold inputs.Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
L
C is a three-level input. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Table 1: CPU Frequency Select Table
Reserved
100.00 33.33 14.318 48.00 96.00
Pin 17 Pin 18
Spread
MHz MHz %
0000
0 0 0 1 100.00 100.00 0.5% Down Spread SRC clocks from SRC_MAIN
0 0 1 0 100.00 100.00 0.5% Down Spread Only SRCCLK1 from PLL3
0 0 1 1 100.00 100.00 1% Down Spread Only SRCCLK1 from PLL3
0 1 0 0 100.00 100.00 1.5% Down Spread Only SRCCLK1 from PLL3
0 1 0 1 100.00 100.00 2% Down Spread Only SRCCLK1 from PLL3
0 1 1 0 100.00 100.00 2.5% Down Spread Only SRCCLK1 from PLL3
0111
N/A N/A N/A N/A
1 0 0 0 24.576 24.576 None 24.576Mhz on SE1 and SE2
1 0 0 1 24.576 98.304 None 24.576Mhz on SE1, 98.304Mhz on SE2
1 0 1 0 98.304 98.304 None 98.304Mhz on SE1 and SE2
1 0 1 1 27.000 27.000 None 27Mhz on SE1 and SE2
1 1 0 0 25.000 25.000 None 25Mhz on SE1 and SE2
1101
N/A N/A N/A N/A
1110
N/A N/A N/A N/A
1111
N/A N/A N/A N/A
B1b1B1b4 B1b3 B1b2
Table 2: PLL3 Quick Confi
uration
onl
a
lies in Mode 0, see Table 6
Comment
PLL 3 disabled
