IDT
TM
56-pin CK505 for Embedded Intel Systems 1614B—01/21/10
ICS9EPRS525
6
56-pin CK505 for Embedded Systems
1
Signal is required to be monotonic in this region.
2
input leakage current does not include inputs with pull-up or pull-down resistors
4
Intentionally blank
7
Operation under these conditions is neither implied, nor guaranteed.
8
Frequency Select pins which have tri-level input
9
PCI3/CFG0 is optional
10
If present. Not all parts have this feature.
5
Maximum VIH is not to exceed VDD
6
Human Body Model
3
3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if s elec ted.
NOTES on Input/Supply/Common Output DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
Clock Jitter Specs - Low Power Differential Outputs
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES
CPU Jitter - Cycle to Cycle CPUJC2C Differential Measurement 85 ps 1
SRC Jitter - Cycle to Cycle SRCJC2C Differential Measurement 125 ps 1
DOT Jitter - Cycle to Cycle DOTJC2C Differential Measurement 250 ps 1
1
Jitter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance
will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver
NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES
Rising Edge Slew Rate tSLR Averaging on 2.5 4 V/ns 2, 3
Falling Edge Slew Rate tFLR Averaging on 2.5 4 V/ns 2, 3
Slew Rate Variation tSLVAR Averaging on 20 % 1, 10
Differential Voltage Swing VSWING Averaging off 300 mV 2
Crossing Point Voltage VXABS Averaging off 300 550 mV 1,4,5
Crossing Point Variation VXABSVAR Averaging off 140 mV 1,4,9
Maximum Output Voltage VHIGH Averaging off 1150 mV 1,7
Minimum Output Voltage VLOW Averaging off -300 mV 1,8
Duty Cycle DCYC Averaging on 45 55 % 2
CPU[1:0] Skew CPUSKEW10 Differential Measurement 100 ps 1
CPU[2_ITP:0] Skew CPUSKEW20 Differential Measurement 150 ps 1
SRC[10:0] Skew SRCSKEW Differential Measurement 3000 ps 1,6
1
Measurement taken for single ended waveform on a component test board (not in system)
2
Measurement taken from differential waveform on a component test board. (not in system)
3
Slew rate emastured through V_swing voltage range centered about differential zero
4
Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)
6
Total distributed intentional SRC to SRC skew. Maximum allowable interpair skew is 150 ps.
7
The max voltage including overshoot.
8
The min voltage including undershoot.
10
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
9
The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross
induced modulation by setting C_cross_delta to be smaller than V_Cross absolute
5
Only applies to the differential rising edge (Clock rising, Clock# falling)
