9EPRS525AGILF Datasheet 9EPRS525AGLF, 9EPRS525AGILFT, 9EPRS525AGILF | P13-P15

IDT

56-pin CK505 for Embedded Intel Systems 1614B—01/21/10

ICS9EPRS525

56-pin CK505 for Embedded Systems

General SMBus serial interface information for the ICS9EPRS525

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address D2

(H)

• ICS clock will

acknowledge

• Controller (host) sends the beginning byte location = N

• ICS clock will

acknowledge

• Controller (host) sends the data byte count = X

• ICS clock will

acknowledge

• Controller (host) starts sending

Byte N through

Byte N + X -1

• ICS clock will

acknowledge

each byte

one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address D2

(H)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte

location = N

• ICS clock will

acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address D3

(H)

• ICS clock will

acknowledge

• ICS clock will send the data byte count = X

• ICS clock sends

Byte N + X -1

• ICS clock sends

Byte 0 through byte X (if X

(H)

was written to byte 8)

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

ICS (Slave/Receiver)

ACK

stoP bit

X Byte

Index Block Write Operation

Slave Address D2

(H)

Beginning Byte = N

WRite

starT bit

Controller (Host)

Byte N + X - 1

Data Byte Count = X

Beginning Byte N

T starT bit

WR WRite

RT Repeat starT

RD ReaD

Beginning Byte N

Byte N + X - 1

N Not acknowledge

PstoP bit

Slave Address D3

(H)

Index Block Read Operation

Slave Address D2

(H)

Beginning Byte = N

ACK

Data Byte Count = X

ACK

ICS (Slave/Receiver)

Controller (Host)

X Byte

ACK

IDT

56-pin CK505 for Embedded Intel Systems 1614B—01/21/10

ICS9EPRS525

56-pin CK505 for Embedded Systems

Byte 0 FS Readback and PLL Selection Register

Bit Pin Name Description Type 0 1 Default

FSLC CPU Freq. Sel. Bit (Most Significant)

Latch

FSLB CPU Freq. Sel. Bit

Latch

FSLA CPU Freq. Sel. Bit (Least Si

nificant)

Latch

4- iAMT_EN

Set via SMBus or dynamically by CK505 if detects

dynamic M1

RW Legacy Mode iAMT Enabled 0

3 Reserved Reserved RW 0

2 - SRC_Main_SEL Select source for SRC Main RW SRC Main = PLL1 SRC Main = PLL3 Latch

1 - SATA_SEL Select source for SATA clock RW

SATA =

SRC_Main

SATA = PLL2 0

0- PD_Restore

1 = on Power Down de-assert return to last known

state

0 = clear all SMBus configurations as if cold power-

on and go to latches open state

This bit is ignored and treated at '1' if device is in

iAMT mode.

Configuration Not

Saved

Configuration

Saved

Byte 1 DOT96 Select and PLL3 Quick Config Register

Bit Pin Name Description Type 0 1 Default

7 13/14 SRC0_SEL Select SRC0 or DOT96 RW SRC0 DOT96 0

6 - PLL1_SSC_SEL Select 0.5% down or center SSC RW Down spread Center spread Latch

5 PLL3_SSC_SEL Select 0.5% down or center SSC RW Down spread Center spread 0

4 PLL3_CF3 PLL3 Quick Confi

Bit 3 R

3 PLL3_CF2 PLL3 Quick Config Bit 2 RW 0

2 PLL3_CF1 PLL3 Quick Config Bit 1 RW 0

1 PLL3_CF0 PLL3 Quick Confi

Bit 0 R

0 PCI_SEL PCI_SEL RW PCI from PLL1

PCI from

SRC_MAIN

Byte 2 Output Enable Register

Bit Pin Name Description Type 0 1 Default

7REF_OE

Output enable for REF, if disabled output is tri-

stated

RW Output Disabled Output Enabled 1

6 USB_OE Output enable for USB RW Output Disabled Output Enabled 1

5 PCIF5_OE Output enable for PCI5 RW Output Disabled Output Enabled 1

4 PCI4_OE Output enable for PCI4 RW Output Disabled Output Enabled 1

3 PCI3_OE Output enable for PCI3 RW Output Disabled Output Enabled 1

2 PCI2_OE Output enable for PCI2 R

Output Disabled Output Enabled 1

1 PCI1_OE Output enable for PCI1 RW Output Disabled Output Enabled 1

0 PCI0_OE Output enable for PCI0 RW Output Disabled Output Enabled 1

Byte 3 Output Enable Register

Bit Pin Name Description Type 0 1 Default

7 Reserved Reserved RW - - 1

6 Reserved Reserved RW - - 1

5 Reserved Reserved RW - - 1

4 SRC8/ITP_OE Output enable for SRC8 or ITP RW Output Disabled Output Enabled 1

3 SRC7_OE Output enable for SRC7 R

Output Disabled Output Enabled 1

2 SRC6_OE Output enable for SRC6 RW Output Disabled Output Enabled 1

1 SRC5_OE Output enable for SRC5 RW Output Disabled Output Enabled 1

0 SRC4_OE Output enable for SRC4 RW Output Disabled Output Enabled 1

See Table 1 : CPU Frequency Select

Table

See Table 2: PLL3 Quick

Configuration

Only applies if Byte 0, bit 2 = 0.

IDT

56-pin CK505 for Embedded Intel Systems 1614B—01/21/10

ICS9EPRS525

56-pin CK505 for Embedded Systems

Byte 4 Output Enable and Spread Spectrum Disable Register

Bit Pin Name Description Type 0 1 Default

7 SRC3_OE Output enable for SRC3 RW Output Disabled Output Enabled 1

6 SATA/SRC2_OE Output enable for SATA/SRC2 RW Output Disabled Output Enabled 1

5 SRC1_OE Output enable for SRC1 R

Output Disabled Output Enabled 1

4 SRC0/DOT96_OE Output enable for SRC0/DOT96 RW Output Disabled Output Enabled 1

3 CPU1_OE Output enable for CPU1 RW Output Disabled Output Enabled 1

2 CPU0_OE Output enable for CPU0 RW Output Disabled Output Enabled 1

1 PLL1_SSC_ON Enable PLL1's spread modulation RW Spread Disabled Spread Enabled 1

0 PLL3_SSC_ON Enable PLL3's spread modulation RW Spread Disabled Spread Enabled 1

Byte 5 Clock Request Enable/Configuration Register

Bit Pin Name Description Type 0 1 Default

7 CR#_A_EN

Enable CR#_A (clk req),

PCI0_OE must be = 1 for this bit to take effect

RW Disable CR#_A Enable CR#_A 0

6 CR#_A_SEL Sets CR#_A to control either SRC0 or SRC2 RW CR#_A -> SRC0 CR#_A -> SRC2 0

5 CR#_B_EN Enable CR#_B (clk req) RW Disable CR#_B Enable CR#_B 0

4 CR#_B_SEL Sets CR#_B -> SRC1 or SRC4 RW CR#_B -> SRC1 CR#_B -> SRC4 0

3 CR#_C_EN Enable CR#_C (clk req) RW Disable CR#_C Enable CR#_C 0

2 CR#_C_SEL Sets CR#_C -> SRC0 or SRC2 R

CR#_C -> SRC0 CR#_C -> SRC2 0

1 CR#_D_EN Enable CR#_D (clk req) RW Disable CR#_D Enable CR#_D 0

0 CR#_D_SEL Sets CR#_D -> SRC1 or SRC4 RW CR#_D -> SRC1 CR#_D -> SRC4 0

Byte 6 Clock Request Enable/Configuration and Stop Control Register

Bit Pin Name Description Type 0 1 Default

7 CR#_E_EN Enable CR#_E (clk req) -> SRC6 RW Disable CR#_E Enable CR#_E 0

6 CR#_F_EN Enable CR#_F (clk req) -> SRC8 R

Disable CR#_F Enable CR#_F 0

5 Reserved Reserved RW - - 0

4 Reserved Reserved RW - - 0

3 Reserved Reserved R

--0

2 Reserved Reserved RW - - 0

SSCD_STP_CRTL

(SRC1)

If set, SSCD (SRC1) stops with PCI_STOP# RW Free Running

Stops with

PCI_STOP#

assertion

0 SRC_STP_CRTL If set, SRCs (except SRC1) stop with PCI_STOP# RW Free Running

Stops with

PCI_STOP#

assertion

Byte 7 Vendor ID/ Revision ID

Bit Pin Name Description Type 0 1 Default

7 Rev Code Bit 3 R X

6 Rev Code Bit 2 R X

5 Rev Code Bit 1 R X

4 Rev Code Bit 0 R X

3 Vendor ID bit 3 R 0

2 Vendor ID bit 2 R 0

1 Vendor ID bit 1 R 0

0 Vendor ID bit 0 R 1

Vendor ID

ICS is 0001, binary

Revision ID

Vendor specific

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

9EPRS525AGILF

Mfr. #:

Buy 9EPRS525AGILF

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner EMBEDDED 56P CK505 COMPATIBLE

Lifecycle:

New from this manufacturer.

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9EPRS525AGILF

9EPRS525AGILF

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