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M48T59, M48T59Y, M48T59V Operation modes
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Table 4. Write mode AC characteristics
2.3 Data retention mode
With valid V
CC
applied, the M48T59/Y/V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V
CC
falls within the V
PFD
(max), V
PFD
(min) window. All outputs
become high impedance, and all inputs are treated as “don't care.”
Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
PFD
(min), the
user can be assured the memory will be in a write protected state, provided the V
CC
fall time
is not less than t
F
. The M48T59/Y/V may respond to transient noise spikes on V
CC
that
reach into the deselect window during the time the device is sampling V
CC
. Therefore,
decoupling of the power supply lines is recommended.
When V
CC
drops below V
SO
, the control circuit switches power to the internal battery which
preserves data and powers the clock. The internal button cell will maintain data in the
M48T59/Y/V for an accumulated period of at least 7 years when V
CC
is less than V
SO
. As
system power returns and V
CC
rises above V
SO
, the battery is disconnected and the power
supply is switched to external V
CC
. Deselect continues for t
rec
after V
CC
reaches V
PFD
(max).
For more information on Battery Storage Life refer to the Application Note AN1012.
Symbol Parameter
(1)
1. Valid for ambient operating temperature: T
A
= 0 to 70°C; V
CC
= 4.5 to 5.5 V, 4.75 to 5.5 V, or 3.0 to 3.6 V
(except where noted).
M48T59/Y/V
Unit–70
Min Max
t
AVAV
WRITE cycle time 70 ns
t
AVWL
Address valid to WRITE enable low 0 ns
t
AVEL
Address valid to chip enable low 0 ns
t
WLWH
WRITE enable pulse width 50 ns
t
ELEH
Chip enable low to chip enable high 55 ns
t
WHAX
WRITE enable high to address transition 0 ns
t
EHAX
Chip enable high to address transition 0 ns
t
DVWH
Input valid to WRITE enable high 30 ns
t
DVEH
Input valid to chip enable high 30 ns
t
WHDX
WRITE enable high to input transition 5 ns
t
EHDX
Chip enable high to input transition 5 ns
t
WLQZ
(2)(3)
2. C
L
= 5pF (see Figure 13 on page 22).
3. If E
goes low simultaneously with W going low, the outputs remain in the high impedance state.
WRITE enable low to output Hi-Z 25 ns
t
AVWH
Address valid to WRITE enable high 60 ns
t
AVEH
Address valid to chip enable high 60 ns
t
WHQX
(2)(3)
WRITE enable high to output transition 5 ns
