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Clock operations M48T59, M48T59Y, M48T59V
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3.4 Calibrating the clock
The M48T59/Y/V is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested not to exceed 35 PPM (parts per million) oscillator
frequency error at 25°C, which equates to about ±1.53 minutes per month. With the
calibration bits properly set, the accuracy of each M48T59/Y/V improves to better than +1/–
2 PPM at 25°C.
The oscillation rate of any crystal changes with temperature (see Figure 8 on page 15).
Most clock chips compensate for crystal frequency and temperature shift error with
cumbersome “trim” capacitors. The M48T59/Y/V design, however, employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 9 on page 15. The number of times pulses
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five-bit Calibration byte found in the Control Register. Adding
counts speeds the clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order bits (D4-D0) in the Control register
(1FF8h). These bits can be set to represent any value between 0 and 31 in binary form. Bit
D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration.
Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per
minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a
binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be
modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles; for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 PPM of
adjustment per calibration step in the calibration register. Assuming that the oscillator is in
fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration Byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or
–2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M48T59/Y/V may
require. The first involves simply setting the clock, letting it run for a month and comparing it
to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows
the designer to give the end user the ability to calibrate his clock as his environment may
require, even after the final product is packaged in a non-user serviceable enclosure. All the
designer has to do is provide a simple utility that accesses the Calibration Byte.
The second approach is better suited to a manufacturing environment, and involves the use
of the IRQ/
FT pin. The pin will toggle at 512 Hz when the Stop Bit (D7 of 1FF9h) is '0,' the
FT Bit (D6 of 1FFCh) is '1,' the AFE Bit (D7 of 1FF6h) is '0,' and the Watchdog Steering Bit
(D7 of 1FF7h) is '1' or the Watchdog Register is reset (1FF7h = 0).
Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 PPM
oscillator frequency error, requiring a –10 (WR001010) to be loaded into the Calibration
Byte for correction. Note that setting or changing the Calibration Byte does not affect the
Frequency Test output frequency.
The IRQ
/FT pin is an open drain output which requires a pull-up resistor for proper
operation. A 500 - 10 kΩ resistor is recommended in order to control the rise time. The FT
Bit is cleared on power-down.
For more information on calibration, see Application Note AN934, “TIMEKEEPER
Calibration.”
