Obsolete Product(s) - Obsolete Product(s)Obsolete Product(s) - Obsolete Product(s)
M48T59, M48T59Y, M48T59V Clock operations
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3.10 Century bit
Bit D5 and D4 of Clock Register 1FFCh contain the CENTURY ENABLE Bit (CEB) and the
CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or
from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle.
Note: The WRITE Bit must be set in order to write to the CENTURY Bit.
3.11 Initial power-on defaults
Upon application of power to the device, the following register bits are set to a '0' state:
WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; FT (see Tabl e 7 ).
Table 7. Default values
3.12 V
CC
noise and negative going transients
I
CC
transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the V
CC
bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the V
CC
bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 12 on page 20) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V
CC
that drive it to values below V
SS
by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
schottky diode from V
CC
to V
SS
(cathode connected to V
CC
, anode to V
SS
). Schottky diode
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
mount.
Condition W R FT AFE ABE
Watchdog
register
(1)
1. WDS, BMB0-BMB4, RBO, RB1.
Initial power-up
(Battery attach for SNAPHAT)
(2)
2. State of other control bits undefined.
00000 0
Subsequent power-up / RESET
(3)
3. State of other control bits remains unchanged.
00000 0
Power-down
(4)
4. Assuming these bits set to '1' prior to power-down.
00011 0
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Clock operations M48T59, M48T59Y, M48T59V
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Figure 12. Supply voltage protection
AI02169
V
CC
0.1μF DEVICE
V
CC
V
SS
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M48T59, M48T59Y, M48T59V Maximum ratings
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4 Maximum ratings
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 8. Absolute maximum ratings
Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the Battery Back-up
mode.
Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Symbol Parameter Value Unit
T
A
Ambient operating temperature 0 to 70 °C
T
STG
Storage temperature (V
CC
off, oscillator off) –40 to 85 °C
T
SLD
(1)(2)(3)
1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to
exceed 150°C for longer than 30 seconds).
2. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget
not to exceed 180°C for between 90 to 150 seconds).
3. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal
budget not to exceed 245°C for greater than 30 seconds).
Lead solder temperature for 10 seconds 260 °C
V
IO
Input or output voltages –0.3 to 7 V
V
CC
Supply voltage
M48T59/M48T59Y –0.3 to 7
V
M48T59V –0.3 to 4.6
I
O
Output current 20 mA
P
D
Power dissipation 1 W

M48T59Y-70MH1F

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
IC RTC CLK/CALENDAR PAR 28SOH
Lifecycle:
New from this manufacturer.
Delivery:
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