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LPC2292FET144/01,5

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54
LPC2292_2294 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 8 June 2011 10 of 54
NXP Semiconductors
LPC2292/2294
16/32-bit ARM microcontrollers with external memory interface
P0[27]/AIN0/
CAP0[1]/
MAT0[1]
23
[6]
H3
[6]
I AIN0 — ADC, input 0. This analog input is always connected
to its pin.
I CAP0[1] — Capture input for Timer 0, channel 1.
O MAT0[1] — Match output for Timer 0, channel 1.
P0[28]/AIN1/
CAP0[2]/
MAT0[2]
25
[6]
J1
[6]
I AIN1 — ADC, input 1. This analog input is always connected
to its pin.
I CAP0[2] — Capture input for Timer 0, channel 2.
O MAT0[2] — Match output for Timer 0, channel 2.
P0[29]/AIN2/
CAP0[3]/
MAT0[3]
32
[6]
L1
[6]
I AIN2 — ADC, input 2. This analog input is always connected
to its pin.
I CAP0[3] — Capture input for Timer 0, Channel 3.
O MAT0[3] — Match output for Timer 0, channel 3.
P0[30]/AIN3/
EINT3/CAP0[0]
33
[6]
L2
[6]
I AIN3 — ADC, input 3. This analog input is always connected
to its pin.
I EINT3 — External interrupt 3 input.
I CAP0[0] — Capture input for Timer 0, channel 0.
P1[0] to P1[31] I/O Port 1: Port 1 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 1 pins
depends upon the pin function selected via the Pin Connect
Block.
Pins 2 through 15 of port 1 are not available.
P1[0]/CS0
91
[7]
G11
[7]
O CS0 — LOW-active Chip Select 0 signal.
(Bank 0 addresses range 0x8000 0000 to 0x80FF FFFF)
P1[1]/OE 90
[7]
G13
[7]
O OE — LOW-active Output Enable signal.
P1[16]/
TRACEPKT0
34
[7]
L3
[7]
O TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with
internal pull-up.
P1[17]/
TRACEPKT1
24
[7]
H4
[7]
O TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with
internal pull-up.
P1[18]/
TRACEPKT2
15
[7]
F2
[7]
O TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with
internal pull-up.
P1[19]/
TRACEPKT3
7
[7]
D2
[7]
O TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with
internal pull-up.
P1[20]/
TRACESYNC
102
[7]
D12
[7]
O TRACESYNC — Trace Synchronization. Standard I/O port
with internal pull-up.
Note: LOW on this pin while RESET
is LOW, enables pins
P1[25:16] to operate as Trace port after reset.
P1[21]/
PIPESTAT0
95
[7]
F11
[7]
O PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with
internal pull-up.
P1[22]/
PIPESTAT1
86
[7]
H11
[7]
O PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with
internal pull-up.
P1[23]/
PIPESTAT2
82
[7]
J11
[7]
O PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with
internal pull-up.
P1[24]/
TRACECLK
70
[7]
L11
[7]
O TRACECLK — Trace Clock. Standard I/O port with internal
pull-up.
Table 4. Pin description
…continued
Symbol Pin (LQFP) Pin
(TFBGA)
[1]
Type Description
LPC2292_2294 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 8 June 2011 11 of 54
NXP Semiconductors
LPC2292/2294
16/32-bit ARM microcontrollers with external memory interface
P1[25]/EXTIN0 60
[7]
K8
[7]
I EXTIN0 — External Trigger Input. Standard I/O with internal
pull-up.
P1[26]/RTCK 52
[7]
N6
[7]
I/O RTCK — Returned Test Clock output. Extra signal added to
the JTAG port. Assists debugger synchronization when
processor frequency varies. Bidirectional pin with internal
pull-up.
Note: LOW on this pin while RESET is LOW, enables pins
P1[31:26] to operate as Debug port after reset.
P1[27]/TDO 144
[7]
B2
[7]
O TDO — Test Data out for JTAG interface.
P1[28]/TDI 140
[7]
A3
[7]
I TDI — Test Data in for JTAG interface.
P1[29]/TCK 126
[7]
A7
[7]
I TCK — Test Clock for JTAG interface. This clock must be
slower than
1
⁄
6
of the CPU clock (CCLK) for the JTAG
interface to operate.
P1[30]/TMS 113
[7]
D10
[7]
I TMS — Test Mode Select for JTAG interface.
P1[31]/TRST
43
[7]
M4
[7]
I TRST — Test Reset for JTAG interface.
P2[0] to P2[31] I/O Port 2 — Port 2 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 2 pins
depends upon the pin function selected via the Pin Connect
Block.
P2[0]/D0 98
[7]
E12
[7]
I/O D0 — External memory data line 0.
P2[1]/D1 105
[7]
C12
[7]
I/O D1 — External memory data line 1.
P2[2]/D2 106
[7]
C11
[7]
I/O D2 — External memory data line 2.
P2[3]/D3 108
[7]
B12
[7]
I/O D3 — External memory data line 3.
P2[4]/D4 109
[7]
A13
[7]
I/O D4 — External memory data line 4.
P2[5]/D5 114
[7]
C10
[7]
I/O D5 — External memory data line 5.
P2[6]/D6 115
[7]
B10
[7]
I/O D6 — External memory data line 6.
P2[7]/D7 116
[7]
A10
[7]
I/O D7 — External memory data line 7.
P2[8]/D8 117
[7]
D9
[7]
I/O D8 — External memory data line 8.
P2[9]/D9 118
[7]
C9
[7]
I/O D9 — External memory data line 9.
P2[10]/D10 120
[7]
A9
[7]
I/O D10 — External memory data line 10.
P2[11]/D11 124
[7]
A8
[7]
I/O D11 — External memory data line 11.
P2[12]/D12 125
[7]
B7
[7]
I/O D12 — External memory data line 12.
P2[13]/D13 127
[7]
C7
[7]
I/O D13 — External memory data line 13.
P2[14]/D14 129
[7]
A6
[7]
I/O D14 — External memory data line 14.
P2[15]/D15 130
[7]
B6
[7]
I/O D15 — External memory data line 15.
P2[16]/D16 131
[7]
C6
[7]
I/O D16 — External memory data line 16.
P2[17]/D17 132
[7]
D6
[7]
I/O D17 — External memory data line 17.
P2[18]/D18 133
[7]
A5
[7]
I/O D18 — External memory data line 18.
P2[19]/D19 134
[7]
B5
[7]
I/O D19 — External memory data line 19.
P2[20]/D20 136
[7]
D5
[7]
I/O D20 — External memory data line 20.
P2[21]/D21 137
[7]
A4
[7]
I/O D21 — External memory data line 21.
P2[22]/D22 1
[7]
A1
[7]
I/O D22 — External memory data line 22.
P2[23]/D23 10
[7]
E3
[7]
I/O D23 — External memory data line 23.
Table 4. Pin description
…continued
Symbol Pin (LQFP) Pin
(TFBGA)
[1]
Type Description
LPC2292_2294 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 8 June 2011 12 of 54
NXP Semiconductors
LPC2292/2294
16/32-bit ARM microcontrollers with external memory interface
P2[24]/D24 11
[7]
E2
[7]
I/O D24 — External memory data line 24.
P2[25]/D25 12
[7]
E1
[7]
I/O D25 — External memory data line 25.
P2[26]/D26/
BOOT0
13
[7]
F4
[7]
I/O D26 — External memory data line 26.
I BOOT0 — While RESET
is low, together with BOOT1
controls booting and internal operation. Internal pull-up
ensures high state if pin is left unconnected.
P2[27]/D27/
BOOT1
16
[7]
F1
[7]
I/O D27 — External memory data line 27.
I BOOT1 — While RESET
is low, together with BOOT0
controls booting and internal operation. Internal pull-up
ensures high state if pin is left unconnected.
BOOT1:0 = 00 selects 8-bit memory on CS0 for boot.
BOOT1:0 = 01 selects 16-bit memory on CS0 for boot.
BOOT1:0 = 10 selects 32-bit memory on CS0
for boot.
BOOT1:0 = 11 selects internal flash memory.
P2[28]/D28 17
[7]
G2
[7]
I/O D28 — External memory data line 28.
P2[29]/D29 18
[7]
G1
[7]
I/O D29 — External memory data line 29.
P2[30]/D30/
AIN4
19
[6]
G3
[6]
I/O D30 — External memory data line 30.
I AIN4 — ADC, input 4. This analog input is always connected
to its pin.
P2[31]/D31/
AIN5
20
[6]
G4
[6]
I/O D31 — External memory data line 31.
I AIN5 — ADC, input 5. This analog input is always connected
to its pin.
P3[0] to P3[31] I/O Port 3 — Port 3 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 3 pins
depends upon the pin function selected via the Pin Connect
Block.
P3[0]/A0 89
[7]
G12
[7]
O A0 — External memory address line 0.
P3[1]/A1 88
[7]
H13
[7]
O A1 — External memory address line 1.
P3[2]/A2 87
[7]
H12
[7]
O A2 — External memory address line 2.
P3[3]/A3 81
[7]
J10
[7]
O A3 — External memory address line 3.
P3[4]/A4 80
[7]
K13
[7]
O A4 — External memory address line 4.
P3[5]/A5 74
[7]
M13
[7]
O A5 — External memory address line 5.
P3[6]/A6 73
[7]
N13
[7]
O A6 — External memory address line 6.
P3[7]/A7 72
[7]
M12
[7]
O A7 — External memory address line 7.
P3[8]/A8 71
[7]
N12
[7]
O A8 — External memory address line 8.
P3[9]/A9 66
[7]
M10
[7]
O A9 — External memory address line 9.
P3[10]/A10 65
[7]
N10
[7]
O A10 — External memory address line 10.
P3[11]/A11 64
[7]
K9
[7]
O A11 — External memory address line 11.
P3[12]/A12 63
[7]
L9
[7]
O A12 — External memory address line 12.
P3[13]/A13 62
[7]
M9
[7]
O A13 — External memory address line 13.
P3[14]/A14 56
[7]
K7
[7]
O A14 — External memory address line 14.
P3[15]/A15 55
[7]
L7
[7]
O A15 — External memory address line 15.
P3[16]/A16 53
[7]
M7
[7]
O A16 — External memory address line 16.
Table 4. Pin description
…continued
Symbol Pin (LQFP) Pin
(TFBGA)
[1]
Type Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54

LPC2292FET144/01,5

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Buy LPC2292FET144/01,5
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM7 256KF/16KR/2CAN
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New from this manufacturer.
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