LPC2292_2294 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 8 June 2011 45 of 54
NXP Semiconductors
LPC2292/2294
16/32-bit ARM microcontrollers with external memory interface
[1] Except on initial access, in which case the address is set up T
cy(CCLK)
earlier.
[2] T
cy(CCLK)
=
1
⁄
CCLK
.
[3] Latest of address valid, CS
LOW, OE LOW to data valid.
[4] Address valid to data valid.
[5] Earliest of CS
HIGH, OE HIGH, address change to data invalid.
[1] See the LPC2119/2129/2194/2292/2294 User Manual for a description of the WSTn bits.
t
BLSHDNV
BLS HIGH to data invalid
time
[2]
(2 T
cy(CCLK)
) 5-(2 T
cy(CCLK)
)+5 ns
t
CHDV
XCLK HIGH to data valid
time
--10ns
t
CHWEL
XCLK HIGH to WE LOW
time
--10ns
t
CHBLSL
XCLK HIGH to BLS LOW
time
--10ns
t
CHWEH
XCLK HIGH to WE HIGH
time
--10ns
t
CHBLSH
XCLK HIGH to BLS HIGH
time
--10ns
t
CHDNV
XCLK HIGH to data invalid
time
--10ns
Table 12. External memory interface dynamic characteristics
…continued
C
L
=25pF, T
amb
=40
C
Symbol Parameter Conditions Min Typ Max Unit
Table 13. Standard read access specifications
Access cycle Max frequency WST
[1]
setting
WST 0; round up to
integer
Memory access time requirement
standard read
standard write
burst read - initial
burst read - subsequent 3 N/A
f
MAX
2WST1+
t
RAM
20 ns+
--------------------------------
WST1
t
RAM
20 ns+
t
cy CCLK
--------------------------------
2–
t
RAM
t
cy C CLK
2WST1+ 20 ns–
f
MAX
1WST2+
t
WRITE
5 ns+
----------------------------------
WST2
t
WRITE
t
CYC
5+–
t
cy CCLK
-------------------------------------------
t
WRITE
t
cy CCLK
1WST2+ 5 ns–
f
MAX
2WST1+
t
INIT
20 ns+
--------------------------------
WST1
t
INIT
20 ns+
t
cy C CLK
--------------------------------
2–
t
INIT
t
cy CCLK
2WST1+ 20 ns–
f
MAX
1
t
ROM
20 ns+
---------------------------------
t
ROM
t
cy CCLK
20 ns–
