LTC4270BIUKG#PBF Datasheet LTC4270AIUKG#PBF, LTC4271IUF#PBF, LTC4270BIUKG#PBF | P22-P24

LTC4270/LTC4271

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APPLICATIONS INFORMATION

programmed I

LIM

setting once inrush has completed. To

maintain IEEE compliance, I

LIM

should be kept at 425mA

for all Type 1 PDs, and 850mA if a Type 2 PD is detected.

LIM

is automatically reset to 425mA when a port turns off.

Table 6. Example Current Limit Settings

LIM

(mA)

INTERNAL REGISTER SETTING (hex)

SENSE

= 0.5Ω R

SENSE

= 0.25Ω

53 88

106 08 88

159 89

213 80 08

266 8A

319 09 89

372 8B

425 00 80

478 8E

531 92 8A

584 CB

638 10 90

744 D2 9A

850 40 C0

956 4A CA

1063 50 D0

1169 5A DA

1275 60 E0

1488 52 49

1700 40

1913 4A

2125 50

2338 5A

2550 60

2975 52

LIM

Foldback

The LTC4270/LTC4271 features a two-stage foldback circuit

that reduces the port current if the port voltage falls below

the normal operating voltage. This keeps MOSFET power

dissipation at safe levels for typical 802.3af MOSFETs,

even at extended 802.3at power levels. Current limit and

foldback behavior are programmable on a per-port basis.

Table 6 gives examples of recommended I

LIM

settings.

The LTC4270/LTC4271 will support current levels well

beyond the maximum values in the 802.3at specification.

The shaded areas in Table 6 indicate settings that may

require a larger external MOSFET, additional heat sinking,

or setting t

LIM

Enable.

MOSFET Fault Detection

LTC4270/LTC4271 PSE ports are designed to tolerate

significant levels of abuse, but in extreme cases it is pos-

sible for the external MOSFET to be damaged. A failed

MOSFET may short source to drain, which will make the

port appear to be on when it should be off; this condition

may also cause the sense resistor to fuse open, turning

off the port but causing the LTC4270 SENSE pin to rise

to an abnormally high voltage. A failed MOSFET may also

short from gate to drain, causing the LTC4270 GATE pin

to rise to an abnormally high voltage. The LTC4270 OUT,

SENSE and GATE pins are designed to tolerate up to 80V

faults without damage.

If the LTC4270/LTC4271 sees any of these conditions for

more than 180μs, it disables all port functionality, reduces

the gate drive pull-down current for the port and reports

a FET Bad fault. This is typically a permanent fault, but

the host can attempt to recover by resetting the port, or

by resetting the entire chip if a port reset fails to clear the

fault. If the MOSFET is in fact bad, the fault will quickly

return, and the port will disable itself again. The remaining

ports of the LTC4270/LTC4271 are unaffected.

An open or missing MOSFET will not trigger a FET Bad

fault, but will cause a t

START

fault if the LTC4270/LTC4271

attempts to turn on the port.

Port Current Readback

The LTC

4270/LTC4271 measures the current at each port

with an internal A/D converter. Port data is only valid when

the port power is on and reads zero at all other times. The

converter has two modes:

• 100ms mode: Samples are taken continuously and the

measured value is updated every 100ms

LTC4270/LTC4271

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• 1s mode: Samples are taken continuously; a moving

1second average is updated every 100ms

Port Current Policing

The LTC4270/LTC4271 can augment t

CUT

current moni-

toring with a policing function to track the one second

current averages. A port violating the user-specified Port

Police Threshold will be shut off with both a t

CUT

and

Police event recorded. A port current Police event can be

differentiated from a port t

CUT

violation by reading both

events bits; both bits are set for a Police violation while

only the t

CUT

bit is set for t

CUT

timer violations.

Port Voltage Readback

The LTC4270/LTC4271 measures the output voltage at

each port with an internal A/D converter. Port data is

only valid when the port power is on and reads zero at

all other times.

Disconnect

The LTC4270/LTC4271 monitors powered ports to ensure

the PD continues to draw the minimum specified current. A

disconnect timer counts up whenever port current is below

7.5mA (typ), indicating that the PD has been disconnected.

If the t

DIS

timer expires, the port will be turned off and the

disconnect bit in the fault event register will be set. If the

current returns before the t

DIS

timer runs out, the timer

resets. As long as the PD exceeds the minimum current

level more often than t

DIS

, it will remain powered.

Although not recommended, the DC disconnect feature

can be disabled by clearing the corresponding enable bits.

Note that this defeats the protection mechanisms built

into the IEEE specification, since a powered port will stay

powered after the PD is removed. If the still-powered port

is subsequently connected to a non-PoE data device, the

device may be damaged.

The LTC4270/LTC4271 does not include AC disconnect

circuitry, but includes AC Disconnect Enable bits to main-

tain compatibility with the LTC4259A.

If the AC Disconnect

Enable bits are set, DC disconnect will be used.

APPLICATIONS INFORMATION

Masked Shutdown

The LTC4270/LTC4271 provides a low latency port shed-

ding feature to quickly reduce the system load when

required. By allowing a pre-determined set of ports to

be turned off, the current on an overloaded main power

supply can be reduced rapidly while keeping high priority

devices powered. Each port can be configured to high or

low priority; all low-priority ports will shut down within

6.5μs after the MSD pin is pulled low, high priority ports

will remain powered. If a port is turned off via MSD, the

corresponding Detection and Classification Enable bits are

cleared, so the port will remain off until the host explicitly

re-enables detection.

In the LTC4270/LTC4271 chipset the active level of MSD

is register configurable as active high or low. The default

is LTC4266-compatible active low behavior.

Readback

The LTC4270/LTC4271 measures the V

voltage with an

internal 12-bit A/D converter.

General Purpose IO

Two sets of general purpose IO pins are available in the

LTC4270/LTC4271 chipset. The first set of general purpose

IO are GP1 and GP0. These fully bidirectional IO are 3.3V

CMOS IO on the LTC4271 chip.

The second set of general purpose IO pins are XIO1 and

XIO0. These fully bidirectional IO are 4.3V CMOS IO on

the LTC4270 chip.

Code Download

LTC4271 firmware is field-upgradable by downloading

and executing RAM images. RAM images are volatile

and must be re-downloaded after each V

power cycle,

but will remain valid during reset and V

power events.

Contact Linear Technology for code download procedures

and RAM images.

LTC4270/LTC4271

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APPLICATIONS INFORMATION

SERIAL DIGITAL INTERFACE

Overview

The LTC4270/LTC4271 communicates with the host us-

ing a standard SMBus/I

C 2-wire interface. The LTC4270/

LTC4271 is a slave-only device, and communicates with

the host master using the standard SMBus protocols.

Interrupts are signaled to the host via the INT pin. The

Timing Diagrams (Figures 5 through 9) show typical

communication waveforms and their timing relationships.

More information about the SMBus data protocols can be

found at www.smbus.org.

The LTC4270/LTC4271 requires both the V

and V

sup-

ply rails to be present for the serial interface to function.

Bus Addressing

The LTC4270/LTC4271’s primary 7-bit serial bus address

is A

10A

b, with bit 6 controlled by AD6 and the

lower four bits set by the AD3-AD0 pins; this allows up

to 10 LTC4270/LTC4271s, on a single bus. Ten LTC4270/

LTC4271 are equivalent to 30 quad PSEs or 120 ports. All

LTC4270/LTC

4271s also respond to the broadcast address

0110000b, allowing the host to write the same command

(typically configuration commands) to multiple LTC4270/

LTC4271s in a single transaction. If the LTC4270/LTC4271

is asserting the INT pin, it will also respond to the alert

response address (0001100b) per the SMBus specification.

Each LTC4270/LTC4271 is logically composed of three

quads of four ports each. Each quad occupies separate,

contiguous I

C addresses. The AD6, AD3-0 pins set the

address of the base quad while the remaining quads are

consecutively numbered. I

C addresses outside of the

x10xxxxb range are considered illegal and will not respond.

Each internal quad is independent of the other quads, with

the exception of writes to the Chip Reset, MSD Inversion

and General Purpose Input Output registers. These registers

are global in nature and will affect all quads.

Figure 14. Example I

C Bus Addressing

Interrupts and SMBAlert

Most LTC4270/LTC4271 port events can be configured

to trigger an interrupt, asserting the INT pin and alerting

the host to the event. This removes the need for the host

to poll the LTC4270/LTC4271, minimizing serial bus traf-

fic and conserving host CPU cycles. Multiple LTC4270/

LTC4271s can share a common INT line, with the host

using the SMBAlert protocol (ARA

) to determine which

LTC4270/LTC4271 caused an interrupt.

For information on serial bus usage and device configura-

tion and status, refer to the LTC4271 Software Program-

ming documentation.

ISOLATION REQUIREMENTS

IEEE 802.3 Ethernet specifications require that network

segments (including PoE circuitry) be electrically isolated

from the chassis ground of each network interface de-

vice. However, network segments are not required to be

isolated from each other, provided that the segments are

connected to devices residing within a single building on

a single power distribution system.

QUAD 0QUAD 1QUAD 2

LTC4271

AD0

AD1

AD2

AD3

AD6

SCL

SDAIN

SDAOUT

SCL

SDA

AD0

3.3V

AD1

AD2

AD3

AD6

SCL

SDAIN

SDAOUT

C ADDRESS

0100000

0100001

0100010

QUAD 0QUAD 1QUAD 2

LTC4271

C ADDRESS

0100111

0101000

0101001

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LTC4270BIUKG#PBF

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Manufacturer:

Analog Devices Inc.

Description:

Power Switch ICs - POE / LAN PoE+ 25.5W 12-Port PSE Controller (Ethernet interface)

Lifecycle:

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