8N3SV76FC-0113CDI Datasheet 8N3SV76EC-0129CDI8, 8N3SV76LC-0154CDI, 8N3SV76BC-0157CDI8 | P1-P3

DATASHEET

LVPECL Frequency-Programmable VCXO IDT8N3SV76

IDT8N3SV76CCD

General Description

The IDT8N3SV76 is an LVPECL Frequency-Programmable VCXO

with very flexible frequency and pull-range programming capabilities.

The device uses IDT’s fourth generation FemtoClock® NG

technology for an optimum of high clock frequency and low phase

noise performance. The device accepts a 2.5V or 3.3V supply and is

packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm

x 1.55mm package.

The device can be factory-programmed to any frequency in the

range of 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz

to the very high degree of frequency precision of 218Hz or better.

The extended temperature range supports wireless infrastructure,

telecommunication and networking end equipment requirements.

Features

• Fourth Generation FemtoClock® NG technology

• Programmable clock output frequency from 15.476MHz to

866.67MHz and from 975MHz to 1,300MHz

• Frequency programming resolution is 218Hz and better

• Factory-programmable VCXO pull range and control voltage

polarity

• Absolute pull range (APR) programmable from typical ±4.5ppm to

±754.5ppm

• One 2.5V or 3.3V LVPECL clock output

• Output enable control input, LVCMOS/LVTTL compatible

• RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.5ps (typical),

• 2.5V or 3.3V supply voltage

• -40°C to 85°C ambient operating temperature

• Lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm

package

IDT8N3SV76

6-lead ceramic 5mm x 7mm x 1.55mm

package body

CD Package

Top View

Pin Assignment

Block Diagram

5nQ

VC 1

nOE 2

GND 3

OSC

114.285 MHz

÷MINT, MFRAC

PFD

LPF

FemtoClock® NG

VCO

1950-2600MHz

÷N

Configuration Register (ROM)

(Frequency, Pull-range, Polarity)

A/D

Pulldown

÷P

nOE

IDT8N3SV76 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO

IDT8N3SV76CCD

Pin Description and Characteristic Tables

NOTE: Pullup refers to internal input resistors. See Table 2, Pin Character istics, for typical values.

Function Tables

Output EnablenOE

0 (default) Q, nQ outputs are enabled.

1 Q, nQ outputs are in high-impedance state.

NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of

218Hz

or better.

Table 1. Pin Descriptions

Number Name Type Description

1 VC Input VCXO Control Voltage input.

2 nOE Input Pulldown

Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface

levels.

Power Negative power supply.

4, 5

Q, nQ

Output Differential clock output. LVPECL interface levels.

Power Positive power supply.

Table 2. Pin Characteristics

Symbol Parameter Test Conditions Minimum Typical Maximum Units

Input Capacitance

nOE 5.5 pF

VC 10 pF

PULLDOWN

Input Pulldown Resistor 50 k

Table 3A. nOE Configuration

Input

Table 3B. Output Frequency Range

15.476MHz to 866.67MHz

975MHz to 1,300MHz

IDT8N3SV76 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO

IDT8N3SV76CCD

Principles of Operation

The block diagram consists of the internal 3

overtone crystal and

oscillator which provide the reference clock f

XTAL

of 114.285MHz.

The PLL includes the FemtoClock® NG VCO along with the

Pre-divider (P), the feedback divider (M) and the post divider (N). The

P, M, and N dividers determine the output frequency based on the

XTAL

reference. The feedback divider is fractional supporting a huge

number of output frequencies. Internal registers are used to hold up

the factory pre-set configuration setting. The P, M, and N frequency

configurations support an output frequency range of 15.476MHz to

866.67MHz and 975MHz to 1,300MHz.

The devices use the fractional feedback divider with a delta-sigma

modulator

for noise shaping and robust frequency synthesis

capability. The relatively high reference frequency minimizes phase

noise generated by frequency multiplication and allows more efficient

shaping of noise by the delta-sigma modulator. The output frequency

is determined by the 2-bit pre-divider (P), the feedback divider (M)

and the 7-bit post divider (N). The feedback divider (M) consists of

both a 7-bit integer portion (MINT) and an 18-bit fractional portion

(MFRAC) and provides the means for high-resolution frequency

generation. The output frequency f

OUT

is calculated by:

OUT

XTAL

PN

------------- MINT

MFRAC 0.5+

-------------------------------------+=

Frequency Configuration

An order code is assigned to each frequency configuration and the

VCXO pull-range programmed by the factory (default frequencies).

For more information on the available default frequencies and order

codes, please see the Ordering Information Section in this document.

For available order codes, see the FemtoClock NG Ceramic-Package

XO and VCXO Ordering Product Information document.

For more information on programming capabilities of the device for

custom

frequency and pull-range configurations, see the FemtoClock

NG Ceramic 5x7 Module Programming Guide.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

8N3SV76FC-0113CDI

Mfr. #:

Buy 8N3SV76FC-0113CDI

Manufacturer:

Description:

IC OSC VCXO 156.25MHZ 6-CLCC

Lifecycle:

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8N3SV76FC-0113CDI

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