LTC3802
10
3802f
PI FU CTIO S
UUU
(28-Pin SSOP/32-Pin QFN Package)
PHASEMD (Pin 17/Pin 15): Phase Selector Input. This pin
determines the phase relationships between controller␣ 1,
controller 2 and the PLLIN signal. When PHASEMD is
floating, its value is around 2V, and the internal phase-
locked loop synchronizes the falling edge of TG1 to the
falling edge of the PLLIN signal. When PHASEMD is forced
high, PLLIN leads TG1 by 90°. TG1 and TG2 remain at 180°
out of phase independent of the PHASEMD input. When
PHASEMD is forced low, an internal current source dis-
charges the RUN/SS slowly to provide power down track-
ing. Avoid coupling noise into this sensitive pin.
FB2 (Pin 18/Pin 16): Channel 2 Controller Error Amplifier
Input. See FB1.
COMP2 (Pin 19/Pin 17): Channel 2 Controller Error Am-
plifier Output. See COMP1.
V
CC
(Pin 20/Pin 18): Power Supply Input. All the internal
circuits except the switcher output drivers are powered
from this pin. V
CC
should be connected to a low noise 5V
supply and should be bypassed to SGND with at least a
10µF capacitor in close proximity to the LTC3802.
CMPIN2 (Pin 21/Pin 19): Channel 2 Controller Compara-
tors Input. See CMPIN1.
I
MAX2
(Pin 22/Pin 20): Channel 2 Controller Current Limit
Set. See I
MAX1
.
PLLLPF (Pin 23/Pin 21): Phase-Locked Loop Lowpass
Filter. The phase-locked loop’s lowpass filter is tied to this
pin. Alternatively, this pin can be driven with an AC or DC
voltage source to vary the frequency of the internal
oscillator.
PLLIN (Pin 24/Pin 22): Phase-Locked Loop Input/Exter-
nal Synchronization Input to the Phase Detector. The
falling edge of this signal is used for frequency synchro-
nization. When PLLIN floats or shorts to ground, the
controllers free run at 550kHz.
SW2 (Pin 25/Pin 25): Channel 2 Controller Switching
Node. See SW1.
TG2 (Pin 26/Pin 26): Channel 2 Controller Top Gate Drive.
See TG1.
BOOST2 (Pin 27/Pin 27): Channel 2 Controller Top Gate
Driver Supply. See BOOST1.
BG2 (Pin 28/Pin 28): Channel 2 Controller Bottom Gate
Drive. See BG1.
Exposed Pad (Pin 33, QFN Package Only): Exposed Pad
is PGND, must be soldered to PCB.
LTC3802
11
3802f
BLOCK DIAGRA
W
+
+
BURST
+
MAX
V
REF
+ 5%V
REF
– 12mVV
REF
+ 15mV
+
NEG
RESET
+
POS
RESET
+
ERR
I
LIM
÷ 5÷ 100
LOGIC
STOP TOP GATE
DISABLE Burst Mode
OPERATION
SGND
10µA
–1
POWER DOWN
I
MAX1,2
PGND
BG1, 2
PV
CC
SW1, 2
TG1, 2
FCB
CHANNEL 1
SUBCIRCUIT
DUPLICATE FOR
SECOND CONTROLLER
CHANNEL
V
CC
BOOST1, 2
+
PWM
LINE
FEEDFORWARD
COMPENSATION
SOFT-
START
100µs
DELAY
FROM CH2 PGOOD
COMPARATORS
PLL AND OSC
PLLIN
TO CH2
PLLLPF
V
INFF
COMP1, 2
PHASEMD
EXTREF
(QFN PACKAGE
ONLY)
FB1, 2
PGOOD
MPG
V
REF
0.6V
7µA
RUN/SS
FBT
CMPIN1, 2
3802 BD
V
REF
– 10%
CMPIN2
+
V
REF
+ 10%
PGOOD COMPARATORS
+
TRACK
NPG
+
PPG
LTC3802
12
3802f
APPLICATIO S I FOR ATIO
WUUU
Switching Architecture
The LTC3802 includes two step-down (buck) voltage
mode feedback switching regulator controllers. These two
controllers act independently of each other except at start-
up and current limit. For proper power-up sequencing,
channel 1 is designated to be the higher output voltage
channel (see Start-Up Tracking).
Each channel uses two external sychronous N-channel
MOSFETs. A floating topside driver and a simple external
charge pump provide full gate drive to each upper MOSFET.
The controller uses leading edge modulation architecture
to allow extremely low duty cycle and fast load recovery
operation. In a typical LTC3802 switching cycle, the PWM
comparator turns on the top MOSFET and charges up the
output capacitor. Some time later, an internal clock resets
the top MOSFET, turns on the bottom MOSFET and re-
duces the output charging current. The top gate duty cycle
is controlled by the feedback amplifier, which compares
the divided output voltage with an internal reference. This
switching cycle repeats itself at a fixed 550kHz frequency
or in synchronization with an external oscillator.
The internal master clock runs at 550kHz, turning off the
top gate once every 1.8µs. Thus, feedback loop compo-
nents and output inductors and capacitors can be scaled
to a particular operating frequency. Noise generated by the
circuit will always be in a known frequency band, with the
550kHz frequency designed to leave the 455kHz IF band
free of interference. Subharmonic oscillation and slope
compensation, common headaches with constant fre-
quency current mode switchers, are absent in voltage
mode designs like the LTC3802. Two LTC3802 channels
run from a common clock, with the phasing chosen to be
180° from channel 1 to channel 2. This has the effect of
doubling the frequency of the switching pulses seen by the
input bypass capacitor, significantly lowering its RMS
current and reducing the capacitance required.
Feedback Control
Each LTC3802 channel senses the output voltage at V
OUT
with an internal feedback op amp (see Block Diagram).
This is a real op amp with a low impedance output, 80dB
open-loop gain and 10MHz gain-bandwidth product. The
positive input is connected to a level-shifted internal
600mV reference, while the negative input is connected to
the level-shifted FB pin. The output is connected to COMP,
which is in turn connected to the line feedforward circuit
and from there to the PWM generator. To speed up the
overshoot recovery time, the maximum potential at the
COMP pin is internally clamped at a level corresponding to
the maximum top gate duty cycle. Under start-up condi-
tions, RUN/SS controls the COMP pin slew rate.
At steady state, as shown in Figure 1, the output of the
switching regulator is given the following equation
VV
R
R
OUT REF
B
=+
•1
1
Unlike many regulators that use a transconductance (g
m
)
amplifier, the LTC3802 is designed to use an inverting sum-
ming amplifier topology with the FB pin configured as a
virtual ground. This allows the feedback gain to be tightly
controlled by external components, which is not possible
with a simple g
m
amplifier. In addition, the voltage feed-
back amplifier allows flexibility in choosing pole and zero
locations. In particular, it allows the use of “Type 3” com-
pensation, which provides a phase boost at the LC pole
frequency and significantly improves the control loop phase
margin.
In a typical LTC3802 circuit, the feedback loop consists of
the line feedforward circuit, the modulator, the external
inductor, the output capacitor and the feedback amplifier
with its compensation network. All these components
affect loop behavior and need to be accounted for in the
loop compensation. The modulator consists of the PWM
generator, the output MOSFET drivers and the external
MOSFETs themselves. The modulator gain varies linearily
with the input voltage. The line feedforward circuit com-
pensates for this change in gain, and provides a constant
gain from the error amplifier output to the inductor input
regardless of input voltage. From a feedback loop point of
view, the combination of the line feedforward circuit and
the modulator looks like a linear voltage transfer function
from COMP to the inductor input and has a gain roughly
equal to 22V/V. It has fairly benign AC behavior at typical
loop compensation frequencies with significant phase
shift appearing at half the switching frequency.

LTC3802EGN#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2-Phase, Dual, Step Dwn Synch Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union