LTC3802
9
3802f
FBT (Pin 8/Pin 5): Feedback Tracking Input. FBT should be
connected through a resistive divider network to V
OUT1
to
set the channel 1 output slew rate. Upon power-up/-down,
the LTC3802 servos FBT and CMPIN2 to the same poten-
tial to control the output power-up/-down slew rate. To
program both outputs to have the same slew rate, dupli-
cate the CMPIN2 resistive divider at FBT. To have a
ratiometric slew rate, short FBT to CMPIN1. To disable the
tracking function, short FBT to CMPIN2.
CMPIN1 (Pin 9/Pin 6): Channel 1 Controller Comparators
Input. CMPIN1 should be connected through a resistive
divider network to V
OUT1
to monitor its real time output
voltage. To improve transient response, a feedforward
capacitor can be added to the resistive divider. The power
good comparators, overvoltage comparator and Burst
reset comparators monitor this node directly. CMPIN1 is
a sensitive pin, avoid coupling noise into this pin.
COMP1 (Pin 10/Pin 7): Channel 1 Controller Error Ampli-
fier Output. The COMP1 pin is connected directly to the
channel 1 error amplifier output and the input of the line
feedforward circuit. Use an RC network between the
COMP1 pin and the FB1 pin to compensate the feedback
loop for optimum transient response. Under start-up
conditions, the potential at RUN/SS controls the slew rate
at COMP1.
FB1 (Pin 11/Pin 8): Channel 1 Controller Error Amplifier
Input. FB1 should be connected through a resistive divider
network to V
OUT1
to set the channel 1 switcher output
voltage. Also, connect the channel 1 switcher loop com-
pensation network to FB1.
SGND (Pin 12/Pin 9): Signal Ground. All the internal low
power circuitry returns to the SGND pin. Connect to a low
impedance ground, separated from the PGND node. All
feedback, compensation and soft-start connections should
return to SGND. SGND and PGND should be connected
only at a single point, near the PGND pin and the negative
terminal of the V
IN
bypass capacitor.
PI FU CTIO S
UUU
(28-Pin SSOP/32-Pin QFN Package)
FCB (Pin 13/Pin 10): Force Continuous Bar. Internally
pulled high. When FCB is shorted to GND, the controller
forces both converters to maintain continuous synchro-
nous operation regardless of load current.
EXTREF (Pin 11, QFN Package Only): External Reference.
The EXTREF pin and the internal bandgap voltage are used
as the switcher control loop’s reference in a diode OR
manner. If the potential at the EXTREF pin is less than 0.6V,
it overrides the internal reference and lowers the switcher
output voltages. If EXTREF potential is more than 1V, the
internal bandgap voltage controls both channel output
voltages. EXTREF has no effect on the PGOOD threshold.
EXTREF is internally connected to the RUN/SS pin in the
GN28 package.
RUN/SS (Pin 14/Pin 12): Run Control and Soft-Start
Input. An internal 7µA current source pull-up and an
external capacitor to ground at this pin sets the start-up
delaly (approximately 300ms/µF), the output ramp rate
and the time delay for soft current limit. Forcing this pin
below 0.8V with an open-drain/collector transistor shuts
down the device. Pulling RUN/SS high with a current
greater than 10µA can result in malfunctioning of tracking
during start-up. Pulling RUN/SS high with currents higher
than 50µA can interfere with current limit protection.
PGOOD (Pin 15/Pin 13): Open-Drain Power Good Output.
PGOOD is pulled to ground under shutdown condition or
when any switcher output voltage is not within ±10% of its
set point .
V
INFF
(Pin 16/Pin 14): Line Feedforward Compensation
Input. Connects to the V
IN
power supply to provide line
feedforward compensation. A change in V
IN
immediately
modulates the input to the PWM comparator and changes
the pulse width in an inversely proportional manner, thus
bypassing the feedback loop and providing excellent tran-
sient line regulation. V
INFF
is a sensitive pin, an external
lowpass filter can be added to this pin to prevent noisy
signals from affecting the loop gain.
