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LTC3802EUH#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
LTC3802
13
3802f
The external inductor/output capacitor combination makes
a more significant contribution to loop behavior. These
components cause a second order LC roll-off at the output
with 180° phase shift. This roll-off is what filters the PWM
waveform, resulting in the desired DC output voltage, but
this phase shift causes stability issues in the feedback loop
and must be frequency compensated. At higher frequen-
cies, the reactance of the output capacitor will approach its
ESR, and the roll-off due to the capacitor will stop, leaving
–20dB/decade and 90° of phase shift.
Figure 1 shows a Type 3 amplifier. The transfer function of
this amplifier is given by the following equation:
V
V
sC R s R R C
sR C C s C C R sC R
COMP
OUT
=
+
()
++
[]
+
()
+
[]
+
()
–()
(//)
1121 133
11 21 1 221 33
The RC network across the error amplifier and the
feedforward components R3 and C3 introduce two pole-
zero pairs to obtain a phase boost at the system unity gain
frequency, f
C
. In theory, the zeros and poles are placed
symmetrically around f
C
, and the spread between the
zeros and the poles is adjusted to give the desired phase
boost at f
C
. However, in practice, if the crossover fre-
quency is much higher than the LC double-pole frequency,
this method of frequency compensation normally gener-
ates a phase dip within the unity bandwidth and creates
some concern regarding conditional stability.
If conditional stability is a concern, move the error
amplifier’s zero to a lower frequency to avoid excessive
phase dip. The following equations can be used to com-
pute the feedback compensation components value:
f Switching frequency
f
LC
f
RC
SW
LC
OUT
ESR
ESR OUT
=
=
π
=
π
1
2
1
2
choose:
Required error amplifier gain at frequency f
C
:
≈+
+
()
≈
+
++
++
40 1 20 1 20
20
2
1
11
1
22
222
2
log – log – log
log •
–
–
() () ()
()
f
f
f
f
A
R
R
f
f
f
f
ff
f
f
f
f
ff
C
LC
C
ESR
MOD
LC
C
P RES
C
P RES Z RES
Z RES
C
ESR
LC
ESR LC
11
2
+
f
f
P RES
C
()
where A
MOD
is the modulator and line feedforward gain
and is equal to:
A
VDC
V
VV
MOD
IN MAX MAX
SAW
≈=≈
()
•
•.
.
/
30 0 89
12
22
Once the value of resistor R1, poles and zeros location
have been decided, the value of R2, C1, C2, R3 and C3 can
be obtained from the above equations.
APPLICATIO S I FOR ATIO
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Figure 1. Type 3 Amplifier Compensation
–
+
V
OUT
V
REF
R1 R3
C3
R2
C1
GAIN (dB)
C2
FB
R
B
COMP
FREQ
–1
–1+1
GAIN
PHASE
BOOST
0
PHASE (DEG)
–90
–180
–270
–380
3802 F01
f Crossover frequency
f
ff
RC
f
f
RRC
ff
RC C
ff
RC
C
SW
ZERR LC
ZRES
C
P ERR ESR
P RES C
==
==
π
==
π+
()
==
π
==
π
10
1
221
5
1
2133
1
221 2
5
1
233
1
2
1
2
()
()
()
()
(//)
LTC3802
14
3802f
CMPIN is also used as the input for the positive power good
comparator PPG and the negative power good comparator
NPG. The PPG comparator goes high if the potential at
CMPIN is 10% above the nominal value. The NPG compara-
tor fires if CMPIN potential is 10% lower than the nominal
value. The output of PPG and NPG is connected to the
PGOOD pin through the transistor MPG (see Block Dia-
gram). PGOOD is an open-drain output and requires an
external pull-up resistor. If channel 1 and 2 regulator out-
put voltages are within ±10% of their nominal values, the
transistor MPG shuts off and PGOOD is pulled high by the
external pull-up resistor. If any of the two outputs is out-
side the 10% window for more than 100µs, PGOOD pulls
low indicating that at least one output is out of regulation.
For PGOOD to go high, both switcher outputs must be in
regulation. PGOOD remains active during soft-start and cur-
rent limit. Upon power-up, PGOOD is forced low. As soon
as the RUN/SS pin rises above the shutdown threshold, the
power good comparators take over and control the transis-
tor MPG directly. The 100µs delay ensures that short out-
put transient glitches that are successfully “caught” by the
power good comparators don’t cause momentary glitches
at the PGOOD pin.
Current Limit Protection
The LTC3802 includes an onboard current limit circuit that
limits the maximum output current to a user-programmed
level. It works by sensing the voltage drop across QB when
QB is on and comparing that voltage to a user-pro-
grammed voltage at I
MAX
. The I
MAX
pin includes a trimmed
10µA pull-up, enabling the user to set the voltage at I
MAX
with a single resistor, R
IMAX
, to ground. The current
comparator reference input is equal to V
IMAX
divided by 5
(see Block Diagram).
Any time QB is on and the current flowing to the output is
reasonably large, the SW node at the drain of QB will be
somewhat negative with respect to PGND. Since QB looks
like a low value resistor during its on-time, the voltage
drop across it is proportional to the current flowing in it.
The LTC3802 senses this voltage, inverts it and compares
it to the current comparator reference. The current com-
parator begins limiting the output current when the mag-
nitude of the negative voltage is larger than its reference.
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Compensating a switching power supply feedback loop is
a complex task. The applications shown in this data sheet
show typical values, optimized for the power components
shown. Though similar power components should suf-
fice, substantially changing even one major power com-
ponent may degrade performance significantly. Stability
also may depend on circuit board layout. To verify the
calculated component values, all new circuit designs
should be prototyped and tested for stability.
Overvoltage Protection and Power Good Flag
Notice that the FB pin is the feedback amplifier’s virtual
ground node (offset by V
REF
). Because the typical com-
pensation network does not include local DC feedback
around the amplifier, the DC level at FB will be an accurate
replica of the output voltage, divided down by the resistive
divider. However, the compensation capacitors will tend
to attenuate AC signals at FB, especially during quick
transients. Because of this delay in the servo loop, the duty
cycle is not able to adjust immediately to shifts in the
output voltage. This problem is most apparent at high
input and low output voltages. Under transient conditions,
a slow reaction in the duty cycle could cause a large step
in the output voltage. The LTC3802 avoids this voltage
instability through the use of an additional comparator
input pin, CMPIN, which provides real time measurement
of the output voltage. A duplicate FB divider, R1 and R
B
should be connected to this pin. A small feedforward
capacitor can be added across the top resistor to speed up
the comparators.
The MAX comparator monitors the output voltage through
the CMPIN pin. If the output moves 5% above its nominal
value, the comparator immediately turns the top MOSFET
(QT) off and the bottom MOSFET (QB) on and maintains
this state until the output falls back within 5% of its nomi-
nal value. This pulls the output down as fast as possible,
preventing damage to the (often expensive) load. If CMPIN
rises because the output is shorted to a higher supply, QB
will stay on until the short goes away, the higher supply
current limits or QB dies trying to save the load. This be-
havior provides maximum protection against overvoltage
fault at the output, while allowing the circuit to resume
normal operation when the fault is removed.
LTC3802
15
3802f
The current limit detector is connected to an internal
100µA current source. Once current limit occurs, this
current begins to discharge the soft-start capacitor at
RUN/SS, reducing the duty cycle and controlling the
output voltage until the current drops below the limit. The
soft-start capacitor needs to move a fair amount before it
has any effect on the duty cycle, adding a delay until the
current limit takes effect. This allows the LTC3802 to
experience brief overload conditions without affecting the
output voltage regulation. The delay also acts as a pole in
the current limit loop to enhance loop stability.
Under severe short-circuit conditions, if the load current is
1.5 times larger than the programmed current limit thresh-
old, the LTC3802 shuts off the top MOSFET immediately.
This stops the increase in the inductor current. At this
moment, if CMPIN is 10% lower than its nominal value, the
LTC3802 hard current limit latches and discharges the
RUN/SS capacitor with a current source of more than 1mA
until RUN/SS hits its shutdown threshold. Once RUN/SS
is completely discharged, the LTC3802 cycles its soft-
start again.
Programming the current limit on the LTC3802 is straight-
forward. To set the current limit, calculate the expected
voltage drop across QB at the maximum desired current:
V
PROG
= (I
LIMIT
)(R
DS(ON)
)
I
LIMIT
should be set much higher than the expected oper-
ating current, to allow for MOSFET R
DS(ON)
changes with
temperature. Power MOSFET R
DS(ON)
varies from MOSFET
to MOSFET, limiting the accuracy obtainable from the
LTC3802 current limit loop. Setting I
LIMIT
to 150% of the
maximum normal operating current is usually safe and will
adequately protect the power components if they are
chosen properly. Note that ringing on the switch node can
cause an error for the current limit threshold. This factor
will change depending on the layout. The SW node should
have minimum routing from the MOSFETs to the LTC3802
to reduce parasitic inductor and hence ringing. V
PROG
is
then programmed at the I
MAX
pin using the internal 10µA
pull-up current and an external resistor:
R
V
A
IMAX
PROG
=
µ
5
10
•
The resulting value of R
IMAX
should be checked in an
actual circuit to ensure that the current circuit kicks in as
expected. Circuits that use very low values for R
IMAX
(<25k) should be checked carefully, since small changes
in R
IMAX
can cause large I
LIMIT
changes when the switch
node ringing makes up a large percentage of the total
V
PROG
value. If V
PROG
is set too low, the LTC3802 may fail
to start up. The LTC3802 current limit is designed prima-
rily as a disaster preventing, “no blow up” circuit, and is
not useful as a precision current regulator.
The LTC3802 bottom MOSFET V
DS
current sensing archi-
tecture not only eliminates the external current sense
resistors and the corresponding power losses in the high
current paths, it allows a wide range of output voltage
setting, including extremely low duty cycle operation. On
the other hand, for high input voltage with small output
inductance applications, care must be taken to avoid
inductor saturation during dead-short conditions. As soon
as the output short circuits, the controller instantaneously
enters maximum duty cycle operation.
During the top MOSFET on interval, the current compara-
tor is not monitoring the current and there is no current
limit action until the bottom MOSFET turns on and the
inductor current exceeds its hard current limit threshold.
Typically, the top MOSFET and the inductor need to
withstand one clock period of transient high current op-
eration until the hard current limit operation engages.
Peak currents can exceed 6 times the maximum DC output
current during this period. Most MOSFETs allow 10µs of
high current and this short duration of current should not
damage the MOSFET. Nevertheless, it is a good idea to
reduce the peak inductor current. This can be achieved by
having a larger inductance to limit the short-circuit current
slew rate, or an inductor with a saturation current that is
higher than the hard current limit threshold. Alternatively,
an inductor core material with a softer saturation charac-
teristic such as iron powder can be used.
Shutdown/Soft-Start
The RUN/SS pin performs two functions: when pulled to
ground it shuts down the LTC3802, and it acts as a
conventional soft-start pin, enforcing a maximum duty
cycle limit proportional to the voltage at RUN/SS. An
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LTC3802EUH#PBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2-Phase, Dual, Step Dwn Synch Controller
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