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LTC3802EUH#PBF

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LTC3802
22
3802f
on-resistance. MOSFET on-resistance is typically speci-
fied with a maximum value R
DS(ON)(MAX)
at 25°C. In this
case, additional margin is required to accommodate the
rise in MOSFET on-resistance due to self heating and
higher ambient temperature:
R
DS(ON)(MAX)
(T) = ρ
T
• R
DS(ON)(MAX)
(25°C)
The ρ
T
term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C as shown in
Figure 8a. For a maximum junction temperature of 100°C,
using a value ρ
T
= 1.3 is reasonable.
MOSFET input capacitance is a combination of several
components but can be taken from the typical “gate
charge” curve included on most data sheets (Figure 8b).
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initial slope is the effect of the gate-to-source and the gate-
to-drain capacitance. The flat portion of the curve is the
result of the Miller multiplication effect of the drain-to-gate
capacitance as the drain drops the voltage across the
current source load. The upper sloping line is due to the
drain-to-gate accumulation capacitance and the gate-to-
source capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given V
DS
drain voltage, but can be
adjusted for different V
DS
voltages by multiplying by the
ratio of the application V
DS
to the curve specified V
DS
values. A way to estimate the C
MILLER
term is to take the
change in gate charge from points a and b on a manufac-
turers data sheet and divide by the stated V
DS
voltage
specified. C
MILLER
is the most important selection criteria
for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. C
RSS
and C
OS
are specified sometimes but definitions of these
parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
TopGateDuty Cycle
V
V
BottomGateDuty Cycle
VV
V
OUT
IN
IN OUT
IN
=
=
–
The power dissipation for the top and bottom MOSFETs at
maximum output current are given by:
P
V
V
IR
V
I
RC
PV V V
f
P
VV
V
IR
TOP
OUT
IN
OUT MAX T TOP DS ON MAX
IN
OUT MAX
DR MILLER
CC TH IL TH IL
sw
BOT
IN OUT
IN
OUT MAX T TOP DS ON MAX
=
()
()( )
+
()( )
+
=
()
()(
() () ()()
()
() ()
() () ()()
•
–
•
–
2
2
2
2
11
ρ
ρ
))
where:
R
DR
= Effective top driver resistance
V
TH(IL)
= MOSFET data sheet specified typical gate
threshold voltage at the specified drain current
APPLICATIO S I FOR ATIO
WUUU
Figure 8a. Typical MOSFET R
DS(ON)
vs Temperature
JUNCTION TEMPERATURE (°C)
–50
ρ
T
NORMALIZED ON-RESISTANCE
1.0
1.5
150
0.5
0
0
50
100
2.0
3802 F08a
+
–
V
DS
V
IN
V
GS
MILLER EFFECT
Q
IN
ab
C
MILLER
= (Q
B
– Q
A
)/V
DS
V
GS
V
+
–
3802 F08b
Figure 8b. Gate Charge Characteristics
LTC3802
23
3802f
C
MILLER
= Calulated Miller capacitance using the gate
charge curve from the MOSFET data sheet
f
SW
= Switching frequency
Both MOSFETs have conduction losses (I
2
R) while the
topside N-channel equation includes an additional term
for transition losses, which peak at the highest input
voltage. For V
IN
< 12V, the high current efficiency gener-
ally improves with larger MOSFETs, while for V
IN
> 12V,
the transition losses rapidly increase to the point that the
use of a higher R
DS(ON)
device with lower C
MILLER
actually
provides higher efficiency. The bottom MOSFET losses
are greatest at high input voltage when the top switch duty
factor is low or during a short circuit when the bottom
switch is on close to 100% of the period.
Schottky Diode D1/D2 Selection
The Schottky diode D1 shown in Figure 7 conducts during
the dead time between the conduction of the power
MOSFET switches. It is intended to prevent the body diode
of the bottom MOSFET from turning on and storing a
charge during the dead time, which can cause a modest
(about 1%) efficiency loss. The diode can be rated for
about one half to one fifth of the full load current since it
is on for only a fraction of the duty cycle. In order for the
diode to be effective, the inductance between it and the
bottom MOSFET must be as small as possible, mandating
that these components be placed adjacently.
C
IN
Selection
The input bypass capacitor in an LTC3802 circuit is
common to both channels. The input bypass capacitor
gets exercised in three ways: its ESR must be low enough
to keep the supply drop low as the top MOSFETs turn on,
its RMS current capability must be adequate to withstand
the ripple current at the input, and the capacitance must be
large enough to maintain the input voltage until the input
supply can make up the difference. Generally, a capacitor
(particularly a non-ceramic type) that meets the first two
parameters will have far more capacitance than is required
to keep capacitance-based droop under control.
The input capacitor’s voltage rating should be at least 1.4
times the maximum input voltage. Power loss due to ESR
occurs not only as I
2
R dissipation in the capacitor itself,
but also in overall battery efficiency. For mobile applica-
tions, the input capacitors should store adequate charge
to keep the peak battery current within the manufacturer’s
specifications.
The input capacitor RMS current requirement is simplified
by the multiphase architecture and its impact on the
worst-case RMS current drawn through the input network
(battery/fuse/capacitor). It can be shown that the worst-
case RMS current occurs when only one controller is
operating. The controller with the highest (V
OUT
)(I
OUT
)
product needs to be used to determine the maximum RMS
current requirement. Increasing the output current drawn
from the other out-of-phase controller will actually de-
crease the input RMS ripple current from this maximum
value. The out-of-phase technique typically reduces the
input capacitor’s RMS ripple current by a factor of 30% to
70% when compared to a single phase power supply
solution.
In continuous mode, the source current of the top N-channel
MOSFET is approximately a square wave of duty cycle
V
OUT
/V
IN
. The maximum RMS capacitor current is given
by:
II
VVV
V
RMS OUT MAX
OUT IN OUT
IN
≈
()
()
–
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is com-
monly used for design because even significant devia-
tions do not offer much relief. The total RMS current is
lower when both controllers are operating due to the
interleaving of current pulses through the input capaci-
tors. This is why the input capacitance requirement calcu-
lated above for the worst-case controller is adequate for
the dual controller design.
Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours of life. This makes it
advisable to further derate the capacitor or to choose a
capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. Always consult the
manufacturer if there is any question.
APPLICATIO S I FOR ATIO
WUUU
LTC3802
24
3802f
APPLICATIO S I FOR ATIO
WUUU
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used as
input capacitors, but each has drawbacks: ceramics have
high voltage coefficients of capacitance and may have
audible piezoelectric effects; tantalums need to be surge-
rated; OS-CONs suffer from higher inductance, larger case
size and limited surface mount applicability; and
electrolytics’ higher ESR and dryout possibility require
several to be used. Sanyo OS-CON SVP, SVPD series;
Sanyo POSCAP TQC series or aluminum electrolytic ca-
pacitors from Panasonic WA series or Cornel Dublilier
SPV series, in parallel with a couple of high performance
ceramic capacitors, can be used as an effective means of
achieving low ESR and its big bulk capacitance goal for the
input bypass.
C
OUT
Selection
The selection of C
OUT
is primarily determined by the ESR
required to minimize voltage ripple and load step tran-
sients. The output ripple ∆V
OUT
is approximately bounded
by:
∆≤∆ +
V I ESR
fC
OUT L
SW OUT
1
8• •
where ∆I
L
is the inductor ripple current.
∆I
L
may be calculated using the equation:
∆=
I
V
Lf
V
V
L
OUT
SW
OUT
IN
•
–1
Since ∆I
L
increases with input voltage, the output ripple
voltage is highest at maximum input voltage. Typically,
once the ESR requirement is satisfied, the capacitance is
adequate for filtering and has the necessary RMS current
rating.
Manufacturers such as Sanyo, Panasonic and Cornell
Dublilier should be considered for high performance
through-hole capacitors. The OS-CON semiconductor elec-
trolyte capacitor available from Sanyo has a good
(ESR)(size) product. An additional ceramic capacitor in
parallel with OS-CON capacitors is recommended to offset
the effect of lead inductance.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or transient current
handling requirements of the application. Aluminum elec-
trolytic and dry tantalum capacitors are both available in
surface mount configurations. New special polymer sur-
face mount capacitors offer very low ESR also but have
much lower capacitive density per unit volume. In the case
of tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. Several excellent
output capacitor choices are the Sanyo POSCAP TPD,
POSCAP TPB, AVX TPS, AVX TPSV, the Kemet T510 series
of surface mount tantalums,Kemet AO-CAPs or the Pana-
sonic SP series of surface mount special polymer capaci-
tors available in case heights ranging from 2mm to 4mm.
Other capacitor types include Nichicon PL series and
Sprague 595D series. Consult the manufacturer for other
specific recommendations.
Inductor Selection
The inductor in a typical LTC3802 circuit is chosen prima-
rily for inductance value and saturation current. The induc-
tor should not saturate below the hard current limit
threshold.
The inductor value sets the ripple current, which is
commonly chosen at around 40% of the anticipated full
load current. Lower ripple current reduces core losses in
the inductor, ESR losses in the output capacitors and
output voltage ripple. Highest efficiency is obtained at low
frequency with small ripple current. However, achieving
high efficiency requires a large inductor and generates
higher output voltage excursion during load transients.
There is a tradeoff between component size, efficiency
and operating frequency. Given a specified limit for ripple
current, the inductor value can be obtained using the
following equation:
L
V
fI
V
V
OUT
SW L MAX
OUT
IN MAX
=
∆
•
•–
() ()
1
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
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LTC3802EUH#PBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2-Phase, Dual, Step Dwn Synch Controller
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