Table 4. Mechanical characteristics
Analog acceleration output pin loading = 3.3 nF capacitors on X and Y axes, with 8.2 nF capacitor on Z axis (HBW
configuration)
Analog acceleration output pin loading = 9.1 nF capacitors on X, Y and Z axes (LBW configuration)
No analog acceleration output pin loading other than external BW setting capacitor
No BYP pin loading other than bypass capacitor and 150 μA DC current draw through resistive divider.
1. Limits verified by characterization only.
2. High and Low Bandwidth modes are configured in non-volatile Memory (NVM) at the factory
2.3 Electrical Specifications
Table 5. Electrical characteristics
Parameter Symbol Test Conditions Min Typ Max Unit
Supply voltage
1
V
DD
1.71 2.8 3.6 V
Active supply current I
DD
180 µA
Shutdown supply current I
DD–SD
30 nA
Voltage supplied at BYP pin
1
V
BYP
I
BYP
≤ 150 µA 1.45 1.5 1.55 V
Output impedance (XYZ
outputs)
1
R
O
8 10 12 kΩ
Bandwidth
1, 2, 3
BW
High BW device
2700(XY)
600(Z)
Hz
Low BW device
1100(XY)
600(Z)
BYP output capacitor value C
BYP
External capacitor 70 100 500 nF
Logic high input level on EN, g-
Select, ST pins
1
VIH 0.75 * V
DD
V
DD
V
Logic low input level on EN, g-
Select, ST pins
1
VIL 0 0.3 * V
DD
V
Turn-on time
1, 2, 4
T
ON
660 µs
g-Select transition delay
3
T
g-Select
340 µs
Operating temperature range
1
T
OP
–40 +105 °C
Notes:
Test conditions (unless otherwise noted):
V
DD
= 2.8 V
Output load = 3.3 nF capacitors on X and Y axes, with 8.2 nF capacitor on Z axis (HBW configuration)
Output load = 9.1 nF capacitors on X, Y and Z axes (LBW configuration)
Output loading other than external capacitor: high impedance
No electrical loading on BYP pin other than output capacitor and 150 μA (max)
DC output current for ADC reference input
T = 25°C, ±2 g range (for ±2/8 g product), ±4 g range (for ±4/16 g product)
1. Limits verified by characterization only.
2. Apply VDD first. Then, Turn-on time is defined by the delay between when the EN pin is set to high and the time at
which a pin's output value reaches 90% of its final value.
3. g-Select pin transition from high to low. Time for output value to reach 90% of final value.
Device Characteristics
10
Xtrinsic FXLN83xxQ 3-Axis Low-Power Analog-Output Accelerometer, Rev2.0,
7/2014.
Freescale Semiconductor, Inc.
4. BYP pin is not connected
3 Printed Circuit Board Layout and Device Mounting
Printed Circuit Board (PCB) layout and device mounting are critical to the overall
performance of the design. The footprint for the surface mount packages must be the
correct size as a base for a proper solder connection between the PCB and the
package. This, along with the recommended soldering materials and techniques, will
optimize assembly and minimize the stress on the package after board mounting.
Freescale application note AN1902, "Assembly Guidelines for QFN and DFN
Packages" discusses the QFN package used by the FXLN83xxQ.
3.1 Printed Circuit Board Layout
The following recommendations are a guide to an effective PCB layout. See Figure 5
for footprint dimensions.
The PCB land should be designed with Non-Solder Mask Defined (NSMD) as
shown in Figure 5.
No additional via pattern underneath package.
No components or vias should be placed at a distance less than 2 mm from the
package land area. This may cause additional package stress if it is too close to
the package land area.
Signal traces connected to pads should be as symmetric as possible. Put dummy
traces on the NC pads in order to have same length of exposed trace for all pads.
No copper traces should be on the top layer of the PCB under the package. This
will cause planarity issues with board mount. Freescale QFN sensors are
compliant with Restrictions on Hazardous Substances (RoHS), having halide-free
molding compound (green) and lead-free terminations. These terminations are
compatible with tin-lead (Sn-Pb) as well as tin-silver-copper (Sn-Ag-Cu) solder
paste soldering processes. Reflow profiles applicable to those processes can be
used successfully for soldering the devices.
Printed Circuit Board Layout and Device Mounting
Xtrinsic FXLN83xxQ 3-Axis Low-Power Analog-Output Accelerometer, Rev2.0,
7/2014.
11
Freescale Semiconductor, Inc.
PCB land pad
Solder stencil opening
12X 0.686
12X 0.330
Solder mask opening
Package
Package footprint
Package footprint
3
65
12X 0.35
0.25
3
12X 0.5
0.3
4
1
2024
7
10
Package footprint
Red = Package footprint
Green = Solder paste stencil
Blue = PCB pad
Black = Solder mask opening
12X 0.889
12X 0.533
12X 0.635
12X 0.305
8X 0.325
4X 0.650
8X 0.325
4X 0.650
8X 0.325
4X 0.650
8X 0.325
4X 0.650
12X 0.3105
12X 0.4121
Figure 5. Footprint
3.2 Overview of Soldering Considerations
The information provided here is based on experiments executed on QFN devices.
These experiments cannot represent exact conditions present at a customer site.
Therefore, information herein should be used for guidance purposes only. Process and
design optimizations are recommended to develop an application-specific solution.
With the proper PCB footprint and solder stencil designs, the package will self-align
during the solder reflow process.
Stencil thickness should be 100 or 125 µm.
The PCB should be rated for the multiple lead-free reflow condition with a
maximum 260 °C temperature.
Printed Circuit Board Layout and Device Mounting
12
Xtrinsic FXLN83xxQ 3-Axis Low-Power Analog-Output Accelerometer, Rev2.0,
7/2014.
Freescale Semiconductor, Inc.

BRKOUT-FXLN8361Q

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Sensor Development Tools Acceleration Sensor Development Tools Breakout board FXLN8361Q
Lifecycle:
New from this manufacturer.
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