1.2 Pin Descriptions
2
3
5
6
8
1
1
1
4
7
9
10
12
V
DD
ST
BYP
EN
Y
OUT
X
OUT
GND
g-Select
GND
NC
NC
Z
OUT
Figure 2. Pin locations
Table 1. Pin descriptions
Pin Name Description I/O
1 BYP Internal voltage regulator output capacitor connection Output
2 V
DD
Supply voltage Power
3 ST
1
Self-Test
• When ST pin is logic high, the accelerometer is put into self-test mode.
• When ST pin is logic low, the accelerometer is put into normal operating mode.
Input
4 EN Power enable pin
• When the EN pin is logic low, the accelerometer is shut down, minimizing current
consumption.
• When the EN pin is logic high, the accelerometer is fully functional.
Input
5 g-Select Full Scale Range selection:
For part numbers FXLN8361QR1 & FXLN8371QR1:
• When the g-select pin is logic low, the accelerometer is in ±8 g mode
• When the g-select pin is logic high, the accelerometer is in ±2 g mode
For part numbers FXLN8362QR1 & FXLN8372QR1:
• When the g-select pin is logic low, the accelerometer is in ±16 g mode
• When the g-select pin is logic high, the accelerometer is in ±4 g mode
Input
6 GND Ground Ground
7 GND Ground Ground
8 Z
OUT
Z-axis analog output Output
9 Y
OUT
Y-axis analog output Output
10 X
OUT
X-axis analog output Output
11 NC No internal connection, may be left floating or connected to GND —
12 NC No internal connection, may be left floating or connected to GND —
EP DNC Center pads should not be soldered, refer to Printed Circuit Board Layout and Device Mounting —
General Description
Xtrinsic FXLN83xxQ 3-Axis Low-Power Analog-Output Accelerometer, Rev2.0,
7/2014.
5
Freescale Semiconductor, Inc.
