CY7C1061GN30
16-Mbit (1 M words × 16 bit) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-93680 Rev. *A Revised September 11, 2015
16-Mbit (1 M words × 16 b it) Static RAM
Features
■ High speed
❐ t
AA
= 10 ns
■ Low active power
❐ I
CC
= 90 mA at 100 MHz
■ Low CMOS standby current
❐ I
SB2
= 20 mA (typ)
■ Operating voltages of 2.2 V to 3.6 V
■ 1.0 V data retention
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE
1
and CE
2
features
■ Available in Pb-free 54-pin TSOP II, and 48-ball VFBGA
packages
■ Offered in dual Chip Enable options
Functional Description
The CY7C1061GN30 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE
) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through
A
19
). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O
8
through I/O
15
) is written into the location specified on the
address pins (A
0
through A
19
).
To read from the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE
) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O
8
to I/O
15
. See Truth Table on page 12
for a complete description of Read and Write modes.
The input or output pins (I/O
0
through I/O
15
) are placed in a high
impedance state when the device is deselected (CE
1
HIGH/CE
2
LOW), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
15
16
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
1M x 16
ARRAY
A
0
A
12
A
14
A
13
A
A
A
17
A
18
A
10
A
11
I/O
0
– I/O
7
OE
I/O
8
– I/O
15
CE
1
WE
BLE
BHE
A
9
A
19
CE
2
Logic Block Diagram
