Document Number: 001-93680 Rev. *A Page 8 of 18
AC Switching Characteristics
Over the Operating Range
Parameter
[10]
Description
-10
Unit
Min Max
Read Cycle
t
power
V
CC
(typical) to the first access
[11]
100 – s
t
RC
Read cycle time 10 – ns
t
AA
Address to data valid – 10 ns
t
OHA
Data hold from address change 3 – ns
t
ACE
CE
1
LOW/CE
2
HIGH to data valid – 10 ns
t
DOE
OE LOW to data valid – 5 ns
t
LZOE
OE LOW to low Z
[12]
0–ns
t
HZOE
OE HIGH to high Z
[12]
–5ns
t
LZCE
CE
1
LOW/CE
2
HIGH to low Z
[12]
3–ns
t
HZCE
CE
1
HIGH/CE
2
LOW to high Z
[12]
–5ns
t
PU
CE
1
LOW/CE
2
HIGH to power-up
[13]
0–ns
t
PD
CE
1
HIGH/CE
2
LOW to power-down
[13]
–10ns
t
DBE
Byte enable to data valid – 5 ns
t
LZBE
Byte enable to low Z 0 – ns
t
HZBE
Byte disable to high Z – 6 ns
Write Cycle
[14, 15]
t
WC
Write cycle time 10 – ns
t
SCE
CE
1
LOW/CE
2
HIGH to write end 7 – ns
t
AW
Address setup to write end 7 – ns
t
HA
Address hold from write end 0–ns
t
SA
Address setup to write start 0 – ns
t
PWE
WE pulse width 7–ns
t
SD
Data setup to write end 5 – ns
t
HD
Data hold from write end 0 – ns
t
LZWE
WE HIGH to low Z
[12,13.]
3–ns
t
HZWE
WE LOW to high Z
[12,13.]
–5ns
t
BW
Byte Enable to End of Write 7–ns
Notes
10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use
output loading shown in part (a) of Figure 3 on page 6, unless specified otherwise.
11. t
POWER
gives the minimum amount of time that the power supply is at typical V
CC
values until the first memory access is performed.
12. t
HZOE
, t
HZCE
, t
HZWE
, t
HZBE
, t
LZOE
, t
LZCE
, t
LZWE
, and t
LZBE
are specified with a load capacitance of 5 pF as in (b) of Figure 3 on page 6. Transition is measured when output goes into
high impedance
13. These parameters are guaranteed by design and are not tested.
14. The internal write time of the memory is defined by the overlap of WE
, CE
1
= V
IL
, and CE
2
= V
IH
. Chip enables must be active and WE and byte enables must be
LOW to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal
that terminates the write.
15. The minimum write cycle time for Write Cycle No. 2 (WE
Controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
