REV. B
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a
AD7724
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
Dual CMOS - Modulators
FUNCTIONAL BLOCK DIAGRAM
AVIN(+)
AVIN(–)
BVIN(+)
BVIN(–)
MZERO
GC
BIP
STBY
RESET
DVDD DVDD1 DGND AVDD AGND
ADATA
SCLK
BDATA
XTAL
OFF
XTAL1
XTAL2/MCLK
DVAL
REF1 REF2A REF2B
CLOCK
CIRCUITRY
AD7724
2.5V
REFERENCE
-
MODULATOR A
-
MODULATOR B
CONTROL
LOGIC
FEATURES
13 MHz Master Clock Frequency
0 V to +2.5 V or 1.25 V Input Range
Single Bit Output Stream
90 dB Dynamic Range
Power Supplies
AVDD, DVDD: 5 V 5%
DVDD1: 3 V 5%
Logic Outputs 3 V/5 V Compatible
On-Chip 2.5 V Voltage Reference
48-Lead LQFP
GENERAL DESCRIPTION
This device consists of two seventh order sigma-delta modula-
tors. Each modulator converts its analog input signal into a high
speed 1-bit data stream. The part operates from a 5 V power
supply and accepts a differential input range of 0 V to +2.5 V or
±1.25 V centered about a common-mode bias. The analog inputs
are continuously sampled by the analog modulators, eliminating
the need for external sample-and-hold circuitry. The input
information is contained in the output stream as a density of
ones. The original information can be digitally reconstructed
with an appropriate digital filter.
The part provides an accurate on-chip 2.5 V reference for each
modulator. A reference input/output function is provided to
allow either the internal reference or an external system refer-
ence to be used as the reference source for the modulator.
The device is offered in a 48-lead LQFP package and designed
to operate from –40°C to +85°C.
AD7724* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DOCUMENTATION
Application Notes
AN-202: An IC Amplifier User’s Guide to Decoupling,
Grounding, and Making Things Go Right for a Change
AN-283: Sigma-Delta ADCs and DACs
AN-311: How to Reliably Protect CMOS Circuits Against
Power Supply Overvoltaging
AN-388: Using Sigma-Delta Converters-Part 1
AN-389: Using Sigma-Delta Converters-Part 2
AN-397: Electrically Induced Damage to Standard Linear
Integrated Circuits:
Data Sheet
AD7724: Dual CMOS Sigma-Delta Modulators Data Sheet
TOOLS AND SIMULATIONS
Sigma-Delta ADC Tutorial
REFERENCE MATERIALS
Technical Articles
Delta-Sigma Rocks RF, As ADC Designers Jump On Jitter
MS-2210: Designing Power Supplies for High Speed ADC
Part 1: Circuit Suggestions Using Features and
Functionality of New Sigma-Delta ADCs
Part 2: Circuit Suggestions Using Features and
Functionality of New Sigma-Delta ADCs
DESIGN RESOURCES
AD7724 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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REV. B
–2–
AD7724–SPECIFICATIONS
1
(AVDD = 5 V 5%; DVDD = 5 V 5%, DVDD1 = 3 V 5%; AGND = DGND = 0 V,
f
MCLK
= 13 MHz ac-coupled sine wave, REF2A = REF2B = 2.5 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Parameter A Version Unit Test Conditions/Comments
STATIC PERFORMANCE When Tested with Ideal FIR Filter as in Figure 1
Integral Nonlinearity ±0.003 % FSR typ
Offset Error ±0.24 % FSR typ
Gain Error
2
±0.6 % FSR typ
Offset Error Drift ±37.69 µV/°C typ
Gain Error Drift REF2 Is an Ideal Reference, REF1 = AGND
Unipolar Mode ±37.69 µV/°C typ
Bipolar Mode ±18.85 µV/°C typ
ANALOG INPUTS
Signal Input Span (VIN(+) – VIN(–))
Bipolar Mode ±V
REF2
/2 V max BIP = V
IH
Unipolar Mode 0 to V
REF2
V max BIP = V
IL
Maximum Input Voltage AVDD V
Minimum Input Voltage 0 V
Input Sampling Capacitance 2 pF typ
Input Sampling Rate 2 f
MCLK
MHz
Differential Input Impedance 10
9
/(8 f
MCLK
)k typ
REFERENCE INPUTS
REF1 Output Voltage 2.32 to 2.68 V min/max
REF1 Output Voltage Drift 60 ppm/°C typ
REF1 Output Impedance 4 k typ
Reference Buffer Offset Voltage ±12 mV max Offset Between REF1 and REF2
Using Internal Reference
REF2 Output Voltage 2.32 to 2.68 V min/max
REF2 Output Voltage Drift 60 ppm/°C typ
Using External Reference REF1 = AGND
REF2 Input Impedance 10
9
/(16 f
MCLK
)k typ
External Reference Voltage Range 2.32 to 2.68 V min/max Applied to REF1 or REF2
DYNAMIC SPECIFICATIONS
3
When Tested with Ideal FIR Filter as in Figure 1
Bipolar Mode BIP = V
IH
, V
CM
= 2.5 V, VIN(+) = VIN(–) = 1.25 V p-p
or VIN(–) = 1.25 V, VIN(+) = 0 V to 2.5 V
Signal-to-(Noise + Distortion) 90 dB typ Input BW = 0 kHz–94.25 kHz
86 dB min
Total Harmonic Distortion –90 dB max Input BW = 0 kHz–94.25 kHz
Spurious Free Dynamic Range –90 dB max Input BW = 0 kHz–94.25 kHz
Unipolar Mode BIP = V
IL
, VIN(–) = 0 V, VIN(+) = 0 V to 2.5 V
Signal-to-(Noise + Distortion) 88 dB typ Input BW = 0 kHz–94.25 kHz
Total Harmonic Distortion –90 dB typ Input BW = 0 kHz–101.556 kHz
Spurious Free Dynamic Range –90 dB typ Input BW = 0 kHz–101.556 kHz
Intermodulation Distortion –93 dB typ
AC CMRR 96 dB typ VIN(+) = VIN(–) = 2.5 V p-p, V
CM
= 1.25 V to
3.75 V, 20 kHz
CLOCK
Square Wave
4
MCLK Duty Ratio 45 to 55 % max For Specified Operation
V
MCLKH
, MCLK High Voltage 4 V min MCLK Uses CMOS Logic
V
MCLKL
, MCLK Low Voltage 0.4 V max
Sine Wave
XTAL1 Voltage Swing 0.4 V p-p min XTAL_OFF Tied Low
4 V p-p max
LOGIC INPUTS
V
IH
, Input High Voltage 2.4 V min
V
IL
, Input Low Voltage 0.8 V max
I
INH
, Input Current 10 µA max
C
IN
, Input Capacitance 10 pF max

AD7724ASTZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized Dual 7th-Order Modulator
Lifecycle:
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