REV. B
AD7724
–6–
PIN FUNCTION DESCRIPTIONS
Mnemonic Description
AVDD Analog Positive Supply Voltage, 5 V ± 5%.
AGND Ground reference point for analog circuitry.
AVIN(–), AVIN(+) Analog Input to Modulator A. In unipolar operation, the analog input range on AVIN(+) is AVIN(–) to
(AVIN(–) + VREF); for bipolar operation, the analog input range on AVIN(+) is (AVIN(–) ± VREF/2). The
absolute analog input range must lie between 0 and AVDD. The input range is continuously sampled and pro-
cessed by the analog modulator.
STBY Standby, Logic Input. When STBY is high, the device is placed in a low power mode. When STBY is low, the
device is powered up.
MZERO Digital Control Input. When MZERO is high, the modulator inputs are internally grounded i.e. tied to AGND
in unipolar mode and REF2 in bipolar mode. MZERO allows on-chip offsets to be calibrated out. MZERO is
low for normal operation.
RESET Reset Logic Input. RESET is an asynchronous input. When RESET is taken high, the sigma-delta modulator is
reset by shorting the integrator capacitors in the modulator. DVAL goes low for 20 MCLK cycles while the
modulator is being reset.
XTAL1 Input to Crystal Oscillator Amplifier. This pin can also be used to gain up a small input square or sine wave
with XTAL_OFF tied low (see Figure 32 on page 12). When a clock source is applied to XTAL1, SCLK will
be inverted and the XTAL1_CLK to SCLK delay will be typically 14 ns longer than t
DELAY
.
XTAL2/MCLK Clock Input. An external clock source can be applied directly to this pin with XTAL_OFF tied high. In this
case, XTAL1 should be tied to AGND. Alternatively, a parallel resonant fundamental frequency crystal, in
parallel with a 1 M resistor, can be connected between XTAL1 and XTAL2 with XTAL_OFF tied low. Exter-
nal capacitors are then required from the XTAL1 and XTAL2 pins to ground. Consult the crystal
manufacturer's recommendation for the load capacitors.
A sine wave can also be used to provide the clock. A sine wave with a voltage swing between 0.4 V p-p and
4 V p-p is needed. XTAL_OFF is tied low and a 1 M resistor is needed between XTAL1 and XTAL2. A
22 pF capacitor is connected in parallel with this resistor. The sine wave is ac coupled to XTAL1 using a
120 pF capacitor. The use of a sine wave to generate the clock eliminates the need for a square wave clock
source which introduces noise.
DVDD Digital Supply Voltage, 5 V ± 5%.
DGND Ground reference for the digital circuitry.
ADATA Modulator A Bit Stream. The digital bit stream from the sigma-delta modulator is output at ADATA.
BDATA Modulator B Bit Stream. The digital bit stream from the sigma-delta modulator is output at BDATA.
SCLK Serial Clock, Logic Output. The bit stream from modulator A and modulator B is valid on the rising edge of
ASCLK.
DVDD1 Digital Supply Voltage for the digital outputs. DVDD1 can have a value of 5 V ± 5% or 3 V ± 5% so that the
logic outputs can be 3 V or 5 V compatible.
DVAL Data Valid Logic Output. A logic high on DVAL indicates that the data bit stream from the AD7724 is an
accurate digital representation of the analog voltage at the input to the sigma-delta modulator. The DVAL pin
is set low for 20 MCLK cycles if the analog input is overranged.
XTAL_OFF Oscillator Enable Input. A logic high disables the crystal oscillator amplifier to allow use of an external clock
source. XTAL_OFF is set to a logic low when an external crystal is used between XTAL1 and XTAL2.
BIP Analog Input Range Select, Logic Input. A logic low on this input selects unipolar mode. A logic high selects
bipolar mode.
GC Digital Control Input. When GC is high, the gain error of the modulator can be calibrated.
BVIN(–), BVIN(+) Analog Input to Modulator B. In unipolar operation, the analog input range on BVIN(+) is BVIN(–) to
(BVIN(–) + VREF); for bipolar operation, the analog input range on BVIN(+) is (BVIN(–) ± VREF/2). The
absolute analog input range must lie between 0 and AVDD. The input range is continuously sampled and pro-
cessed by the analog modulator.
REF2B Reference Input/Output to Sigma-Delta Modulator B. REF2B connects to the output of an external buffer amplifier
used to drive sigma-delta modulator B. When REF2B is used as an input, REF1 must be connected to AGND.
REF1 Reference Input/Output. REF1 connects through 3 k to the output of the internal 2.5 V reference and to the
input of two buffer amplifiers that drive Σ- modulator A and Σ- modulator B. The pin can be overdriven with
an external 2.5 V reference.
REF2A Reference Input/Output to Sigma-Delta Modulator A. REF2A connects to the output of an external buffer
amplifier used to drive sigma-delta modulator A. When REF2A is used as an input, REF1 must be connected
to AGND.
REV. B
AD7724
–7–
TERMINOLOGY (IDEAL FIR FILTER USED WITH AD7724
[FIGURE 1])
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale (not to be con-
fused with bipolar zero), a point 0.5 LSB below the first code
transition (100...00 to 100...01 in bipolar mode and
000...00 to 000...01 in unipolar mode) and full scale, a
point 0.5 LSB above the last code transition (011...10 to
011...11 in bipolar mode and 111...10 to 111...11 in
unipolar mode). The error is expressed in LSBs.
Common-Mode Rejection Ratio
The ability of a device to reject the effect of a voltage applied to
both input terminals simultaneously—often through variation of
a ground level—is specified as a common–mode rejection ratio.
CMRR is the ratio of gain for the differential signal to the gain
for the common-mode signal.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal VIN(+) voltage which is (VIN(–) + 0.5 LSB)
when operating in the unipolar mode.
Bipolar Offset Error
This is the deviation of the midscale transition (111...11
to 000...00) from the ideal VIN(+) voltage which is (VIN(–)
–0.5 LSB) when operating in the bipolar mode.
Gain Error
The first code transition should occur at an analog value 1/2 LSB
above minus full scale. The last code transition should occur for
an analog value 1 1/2 LSB below the nominal full-scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Signal-to-(Noise + Distortion)
Signal-to-(Noise + Distortion) is the measured signal-to-noise
plus distortion ratio at the output of the ADC. The signal is the
rms magnitude of the fundamental. Noise plus distortion is the
rms sum of all of the nonfundamental signals and harmonics up
to half the Output Data Rate (f
O
/2), excluding dc. Signal-to-
(Noise + Distortion) is dependent on the number of quantiza-
tion levels used in the digitization process; the more levels, the
smaller the quantization noise. The theoretical Signal-to-(Noise
+ Distortion) ratio for a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
where N is the number of bits.
Total Harmonic Distortion
THD is the ratio of the rms sum of harmonics to the rms value
of the fundamental. THD is defined as
THD = 20 log
(V
2
2
+V
3
2
+V
4
2
+V
5
2
+V
6
2
)
V
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
and V
6
are the rms amplitudes of the second through the
sixth harmonic.
Spurious Free Dynamic Range
Spurious free dynamic range is the difference, in dB, between
the peak spurious or harmonic component in the ADC output
spectrum (up to f
O
/2 and excluding dc) and the rms value of the
fundamental. Normally, the value of this specification will be
determined by the largest harmonic in the output spectrum of
the FFT. For input signals whose second harmonics occur in
the stop band region of the digital filter, a spur in the noise floor
limits the SFDR.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
REV. B
AD7724
–8–
(AVDD = DVDD = 5.0 V, T
A
= 25C; CLKIN = 13 MHz ac-coupled sine wave, AIN = 20 kHz, Bipolar Mode; V
IN
(+) = 0 V to 2.5 V, V
IN
(–) = 1.25 V
unless otherwise noted)
INPUT LEVEL dB
dB
110
100
50
40 30 0
20 10
90
80
70
60
SFDR
S/ (N+D)
TPC 1. S/(N+D) and SFDR vs.
Analog Input Level
INPUT FREQUENCY kHz
dB
85
90
115
0 20 100
40 60 80
95
100
105
110
THD
SNR
SFDR
V
IN
(+) = V
IN
() = 1.25V p-p
V
CM
= 2.5V
TPC 4. SNR, THD, and SFDR vs.
Input Frequency
TEMPERATURE °C
dB
94
116
50 25 100
0255075
96
108
110
112
114
100
102
106
104
98
THD
3RD
4TH
2ND
TPC 7. THD vs. Temperature
–Typical Performance Characteristics
OUTPUT DATA RATE kSPS
dB
84
92
85
88
89
90
91
86
87
0 50 300
100 150 200 250
AIN = 1/5 BW
TPC 2. S/(N+D) vs. Output Sample
Rate
OUTPUT DATA RATE kSPS
dB
84
92
85
88
89
90
91
86
87
0 50 300
100 150 200 250
AIN = 1/5 BW
V
IN
(+) = V
IN
() = 1.25V p-p
V
CM
= 2.5V
TPC 5. S/(N+D) vs. Output Sample
Rate
CODES
FREQUENCY OF OCCURENCE
5000
0
n3n2 n+3n1 n n+1 n+2
4500
2000
1500
1000
500
4000
3500
2500
3000
V
IN
(+) = V
IN
()
CLKIN = 13MHz
8k SAMPLES
TPC 8. Histogram of Output Codes
with DC Input
INPUT FREQUENCY kHz
dB
85
90
115
0 20 100
40 60 80
95
100
105
110
SNR
SFDR
THD
TPC 3. SNR, THD, and SFDR vs.
Input Frequency
TEMPERATURE °C
92.0
91.5
88.0
50 0 10050
90.0
89.5
88.5
89.0
91.0
90.5
dB
TPC 6. SNR vs. Temperature
CODE
DNL ERROR LSB
1.0
0.8
1.0
0 20000 6553540000
0.4
0.8
0.6
0
0.2
0.6
0.2
0.4
TPC 9. Differential Nonlinearity

AD7724ASTZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized Dual 7th-Order Modulator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet