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AD7724ASTZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
REV. B –3–
AD7724
Parameter A Version Unit Test Conditions/Comments
LOGIC OUTPUTS
V
OH
, Output High Voltage DVDD1 – 0.2 V min |I
OUT
| ≤ 200 µA
V
OL
, Output Low Voltage 0.4 V max |I
OUT
| ≤ 1.6 mA
POWER SUPPLIES
AVDD/DVDD 4.75/5.25 V min/V max
DVDD1 2.85/5.25 V min/V max
I
DD
(Total for AVDD, DVDD) Digital Inputs Equal to 0 V or DVDD
Active Mode 60 mA max
Standby Mode 20 µA max
NOTES
1
Operating temperature range is as follows: A Version: –40°C to +85°C.
2
Gain Error excludes reference error. The modulator gain is calibrated wrt the voltage on the REF2 pin.
3
Measurement Bandwidth = 0.5 × f
MCLK
; Input Level = –0.05 dB.
4
When a square wave clock is used, the dynamic specifications will degrade by 1 dB typically.
Specifications subject to change without notice.
BIT STREAM
94.25kHz
FILTER 1
120dB
304.687kHz
BANDWIDTH = 94.25kHz
TRANSITION = 304.687kHz
ATTENUATION = 120dB
COEFFICIENTS = 384
DECIMATE
BY 32
FILTER 2
16-BIT
OUTPUT
94.25kHz
90dB
108.874kHz
BANDWIDTH = 94.25kHz
TRANSITION = 108.874kHz
ATTENUATION = 90dB
COEFFICIENTS = 151
DECIMATE
BY 2
Figure 1. Digital Filter (Consists of Two FIR Filters). This Filter is Implemented on the AD7722.
REV. B
AD7724
–4–
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
, T
MAX
Parameter (A Version) Unit Conditions/Comments
f
MCLK
100 kHz min Master Clock Frequency
15 MHz max 13 MHz for Specified Performance
t
DELAY
14 ns max MCLK to SCLK Delay
t
1
67 ns min Master Clock Period
t
2
0.45 × t
MCLK
ns min Master Clock Input High Time
t
3
0.45 × t
MCLK
ns min Master Clock Input Low Time
t
4
15 ns min Data Hold Time After SCLK Rising Edge
t
5
10 ns min RESET Pulsewidth
t
6
10 ns min RESET Low Time Before MCLK Rising
t
7
20 × t
MCLK
ns max DVAL High Delay After RESET Low
t
8
3 ns max Data Access Time After SCLK Falling Edge
t
9
t
3
–t
8
ns max Data Valid Time Before SCLK Rising Edge
NOTES
1
Sample tested at 25°C to ensure compliance.
2
Guaranteed by design.
TO
OUTPUT
PIN
C
L
50pF
I
OH
200␮A
I
OL
1.6mA
1.6V
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
t
4
SCLK (O)
DATA (O)
t
1
t
2
t
3
NOTE:
O SIGNIFIES AN OUTPUT
t
8
t
9
Figure 3. Data Timing
t
5
MCLK (I)
RESET (I)
DVAL (O)
t
6
t
7
NOTE:
I SIGNIFIES AN INPUT
O SIGNIFIES AN OUTPUT
Figure 4. RESET Timing
(AVDD = 5 V ⴞ 5%; DVDD = 5 V ⴞ 5%; DVDD1 = 3 V ⴞ 5%; AGND = DGND = 0 V, REF2A =
REF2B = 2.5 V, unless otherwise noted.)
REV. B
AD7724
–5–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7724 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
*
(T
A
= 25°C unless otherwise noted)
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –1 V to +1 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Inputs to DGND . . . . . . . . –0.3 V to DVDD + 0.3 V
Digital Outputs to DGND . . . . . . . –0.3 V to DVDD + 0.3 V
VIN(+), VIN(–) to AGND . . . . . . . –0.3 V to AVDD + 0.3 V
REF1 to AGND . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
REF2 to AGND . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
REFIN to AGND . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AVDD
AGND
BVIN(–)
NC
BVIN(+)
AGND
AVDD
AVDD
AGND
AVIN(–)
NC
AVIN(+)
AGND
AVDD
NC = NO CONNECT
NC
STBY
MZERO
RESET
NC
GC
BIP
XTAL_OFF
AD7724
NC
NC
NC
NC
AGND
REF2A
AGND
REF1
AVDD
NC
REF2B
AGND
NC
NC
NC
XTAL1
XTAL1/MCLK
DVDD
DGND
DGND
ADATA
BDATA
SCLK
DVDD1
DVAL
NC
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD7724AST –40°C to +85°C 48-Lead Plastic Thin Quad Flatpack (LQFP) ST-48
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD7724ASTZ

Mfr. #:
Buy AD7724ASTZ
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized Dual 7th-Order Modulator
Lifecycle:
New from this manufacturer.
Delivery:
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