General Description
The LRDIMM uses the same interface as the standard DDR3 RDIMM, but reduces the
channel loading by buffering all signals that go to the DRAM. Like a standard RDIMM,
the command, control, address, and clocks are redriven by the memory buffer and have
similar characteristics to single-registered RDIMM. Additionally, the LRDIMM buffers
all data and strobes through the memory buffer. This reduces the channel loading, as
there is only a single load per signal, per module, for all DQ and DQS nodes.
The LRDIMM is a high-speed, CMOS dynamic random access memory module that
uses internally configured 8-bank DDR3 SDRAM devices. DDR3 architecture is an 8n-
prefetch architecture with an interface designed to transfer two data words per clock cy-
cle at the I/O pins. A single read or write access for the DDR3 SDRAM module consists
of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and
eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
For improved signal quality, the clock, control, command, and address buses have been
routed in a fly-by topology, where each clock, control, command, and address pin on
each DRAM is connected to a single trace and terminated (rather than a tree structure,
where the termination is off the module near the connector). Inherent to fly-by topolo-
gy, the timing skew between the clock and DQS signals can be easily accounted for by
using the write-leveling feature of DDR3.
LRDIMMs use two sets of differential signals: DQS/DQS# to capture data and CK/CK#
to capture commands, addresses, and control signals. Differential clocks and data
strobes ensure exceptional noise immunity for these signals and provide precise cross-
ing points to capture input signals.
The LRDIMM includes two temperature sensors:
• A temperature sensor located within the memory buffer monitors the temperature of
that high-current device on the PCB.
• A temperature sensor integrated with the serial presence-detect (SPD) EEPROM mon-
itors the temperature of the module PCB directly through a heat paddle under the EE-
PROM.
The DRAM temperature is related to these two indicators by a combination of heat
spreader performance, ambient temperature, and air flow.
Memory Buffer Operation
LRDIMMs provide increased performance by presenting a single memory buffer to the
system, rather than multiple DRAM. Additionally, increased capacity is achieved due to
the well-defined topology and load that is achieved on the module because the memory
buffer drives only the SDRAM.
Four chip selects are possible at the edge connector; however, the memory buffer pro-
vides an address multiplication feature to increase the number of ranks accessible to
the system. The memory buffer uses one or two of the upper chip selects not directly
usable by the SDRAM to generate additional chip selects. This feature is configurable
within the memory buffer.
Control and Status Registers
The memory buffer contains control and status registers. All control and status registers
are accessible through the SMBus, as well as through in-band channel commands. The
16GB (x72, ECC, QR x8) 240-Pin DDR3L LRDIMM
General Description
PDF: 09005aef846600e0
kszf36c2gx72ldz.pdf - Rev. F 9/15 EN
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