registers can be read by software from the SMBus host any time the memory buffer is
powered, except when the memory buffer is in clock-stopped power-down mode, or
when the device RESET# pin is asserted.
Temperature Sensor
The memory buffer contains a class-C temperature sensor that can be configured to as-
sert the EVENT# pin when temperature thresholds are exceeded. The temperature sen-
sor is accessible through the SMBus.
Parity Operations
The memory buffer can accept a parity bit from the system’s memory controller, pro-
viding even parity for the control, command, and address bus. Parity is calculated from
all command and address signals (CKE, ODT, and S# are not included in parity). The last
bit of the sum is compared to the parity signal provided by the system at the Par_In pin.
Parity errors are flagged on the Err_Out# pin. Parity is also checked during control-word
programming.
Serial Presence-Detect EEPROM with Temperature Sensor
Serial Presence-Detect EEPROM Operation
DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with
JEDEC standard JC-45, “Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM
Modules.” These bytes identify module-specific timing parameters, configuration infor-
mation, and physical attributes. User-specific information can be written into the re-
maining 128 bytes of storage. READ/WRITE operations between the system (master)
and the EEPROM (slave) device occur via the SMBus. Write-protect (WP) is connected
to V
SS
, permanently disabling hardware write-protect. For further information please
refer to Micron technical note TN-04-42, "Memory Module Serial Presence-Detect."
Temperature Sensor
A class-B temperature sensor is integrated with the SPD EEPROM component on the
module. The sensor temperature is monitored and converted into a digital word via the
SMBus. System designers can use the user-programmable registers to create a custom
temperature-sensing solution based on system requirements. Programming and config-
uration details comply with JEDEC standard No. 21-C page 4.7-1, “Definition of the
TSE2002av, Serial Presence Detect with Temperature Sensor.”
16GB (x72, ECC, QR x8) 240-Pin DDR3L LRDIMM
General Description
PDF: 09005aef846600e0
kszf36c2gx72ldz.pdf - Rev. F 9/15 EN
13
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in each device's data sheet is not implied. Exposure to ab-
solute maximum rating conditions for extended periods may adversely affect reliability.
Table 8: Absolute Maximum Ratings
Symbol Parameter Min Max Units
V
DD
V
DD
supply voltage relative to V
SS
–0.4 1.975 V
V
IN
, V
OUT
Voltage on any pin relative to V
SS
–0.4 1.975 V
Table 9: Operating Conditions
Symbol Parameter Min Nom Max Units Notes
V
DD
V
DD
supply voltage 1.283 1.35 1.45 V
1.425 1.5 1.575 V 1
V
REFCA(DC)
Input reference voltage command/
address bus
0.49 × V
DD
0.5 × V
DD
0.51 × V
DD
V
V
REFDQ(DC)
I/O reference voltage DQ bus 0.49 × V
DD
0.5 × V
DD
0.51 × V
DD
V
I
VTT
Termination reference current from
V
TT
–600 600 mA
V
TT
Termination reference voltage (DC) –
command/address bus
0.49 × V
DD
- 20mV 0.5 × V
DD
0.51 × V
DD
+ 20mV V 2
T
A
Module ambient
operating temperature
Commercial 0 70 °C 3, 4
T
C
DDR3 SDRAM compo-
nent case operating
temperature
Commercial 0 95 °C 3, 4, 5
Notes:
1. Module is backward compatible with 1.5V operation. Refer to device specification for
details and operation guidance.
2. V
TT
termination voltage in excess of the stated limit will adversely affect the command
and address signals’ voltage margin and will reduce timing margins.
3. T
A
and T
C
are simultaneous requirements.
4. For further information, refer to technical note TN-00-08: “Thermal Applications,”
available on Micron’s web site.
5. The refresh rate is required to double when 85°C < T
C
95°C.
16GB (x72, ECC, QR x8) 240-Pin DDR3L LRDIMM
Electrical Specifications
PDF: 09005aef846600e0
kszf36c2gx72ldz.pdf - Rev. F 9/15 EN
14
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR3 component data sheets.
Component specifications are available at micron.com. Module speed grades correlate
with component speed grades, as shown below.
Table 10: Module and Component Speed Grades
DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade Component Speed Grade
-2G1 -093
-1G9 -107
-1G6 -125
-1G4 -15E
-1G1 -187E
-1G0 -187
-80C -25E
-80B -25
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully de-
signed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level.
Micron encourages designers to simulate the signal characteristics of the system's
memory bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to en-
sure the required supply voltage is maintained.
16GB (x72, ECC, QR x8) 240-Pin DDR3L LRDIMM
DRAM Operating Conditions
PDF: 09005aef846600e0
kszf36c2gx72ldz.pdf - Rev. F 9/15 EN
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.

MT36KSZF1G72LDZ-1G4M1A5

Mfr. #:
Manufacturer:
Micron
Description:
MODULE DDR3L SDRAM 8GB 240LRDIMM
Lifecycle:
New from this manufacturer.
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