LTC4370
16
4370f
Typical applicaTions
Current Sharing 3.3V Supplies for 20A Output
C2
0.1µF
C1
0.1µF
GATE1CPO1
CPO2
GND
EN1
EN2
RANGE
4370 TA02
V
INA
3.3V ±3%
V
INB
3.3V ±3%
R3
20k
OUT
20A
V
IN1
V
CC
FETON1
COMP
FETON2
OUT1
OUT2
GATE2V
IN2
LTC4370
R1
2mΩ
R2
2mΩ
C
C
0.47µF
C
VCC
0.1µF
M2
IRLS3034PBF
M1
IRLS3034PBF
LTC4370
17
4370f
Typical applicaTions
12V Ideal Diode-OR by Tying RANGE to V
CC
(to Compare Against Load Share).
Use LTC4353 if Load Share Is Not Desired
M2
SUM85N03-06P
M1
SUM85N03-06P
GATE1CPO1
NC
NC
CPO2
V
CC
EN1
EN2
GND
4370 TA03
V
INA
12V
V
INB
12V
OUT
10A
V
IN1
RANGE
FETON1
COMP NC
FETON2
OUT1
OUT2
GATE2V
IN2
LTC4370
C
VCC
0.1µF
LTC4370
18
4370f
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1732 Rev Ø)
3.00 ±0.10
(2 SIDES)
4.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ± 0.10
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
3.15 REF
1.70 ± 0.05
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DE16) DFN 0806 REV Ø
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
3.15 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 ±0.05
0.70 ±0.05
3.60 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
3.30 ±0.05
3.30 ±0.10
0.45 BSC
0.23 ± 0.05
0.45 BSC

LTC4370IMS#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Management Specialized - PMIC Two-S Diode-OR C Balancing Cntr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union