CY7C130, CY7C130A
CY7C131, CY7C131A
Document Number: 38-06002 Rev. *H Page 10 of 22
Busy/Interrupt Timing
t
BLA
BUSY LOW from address match 20 25 30 ns
t
BHA
BUSY HIGH from address mismatch
[30]
20 25–30ns
t
BLC
BUSY LOW from CE LOW 20 25 30 ns
t
BHC
BUSY HIGH from CE HIGH
[30]
20 25–30ns
t
PS
Port set-up for priority 5 5 5 ns
t
WB
[31]
R/W LOW after BUSY LOW 0 0 0 ns
t
WH
R/W HIGH after BUSY HIGH 30 35 35 ns
t
BDD
BUSY HIGH to valid data 35 45 45 ns
t
DDD
Write data valid to read data valid Note 32 Note 32 Note 32 ns
t
WDD
Write pulse to data delay Note 32 Note 32 Note 32 ns
Interrupt Timing
t
WINS
R/W to INTERRUPT set time 25 35 45 ns
t
EINS
CE to INTERRUPT set time 25 35 45 ns
t
INS
Address to INTERRUPT set time 25 35 45 ns
t
OINR
OE to INTERRUPT reset time
[20]
25 35–45ns
t
EINR
CE to INTERRUPT reset time
[20]
25 35–45ns
t
INR
Address to INTERRUPT reset time
[20]
25 35–45ns
Switching Characteristics
Over the Operating Range
[23, 24]
(continued)
Parameter Description
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55
Unit
Min Max Min Max Min Max
Notes
30. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
31. CY7C140/CY7C141 only.
32. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY
on Port B goes HIGH.
Port B’s address is toggled.
CE
for Port B is toggled.
R/W for Port B is toggled during valid read.
CY7C130, CY7C130A
CY7C131, CY7C131A
Document Number: 38-06002 Rev. *H Page 11 of 22
Switching Waveforms
Figure 5. Read Cycle No. 1
[33, 34]
Figure 6. Read Cycle No. 2
[33, 35]
Figure 7. Read Cycle No. 3
[34]
Notes
33. R/W
is HIGH for read cycle.
34. Device is continuously selected, CE
= V
IL
and OE =
V
IL
.
35. Address valid prior to or coincident with CE
transition LOW.
t
RC
t
AA
t
OHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
Either Port Address Access
t
ACE
t
LZOE
t
DOE
t
HZOE
t
HZCE
DATA VALID
DATA OUT
CE
OE
t
LZCE
t
PU
I
CC
I
SB
t
PD
Either Port CE/OE Access
t
BHA
t
BDD
VALID
t
DDD
t
WDD
ADDRESS MATCH
ADDRESS MATCH
R/W
R
ADDRESS
R
D
INR
ADDRESS
L
BUSY
L
DOUT
L
t
PS
t
BLA
Read with BUSY, Master: CY7C130 and CY7C131
t
RC
t
PWE
VALID
t
HD
CY7C130, CY7C130A
CY7C131, CY7C131A
Document Number: 38-06002 Rev. *H Page 12 of 22
Figure 8. Write Cycle No. 1 (OE Three-States Data I/Os—Either Port
[36, 37]
Figure 9. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)
[38, 39]
Switching Waveforms (continued)
t
AW
t
WC
DATA VALID
HIGH IMPEDANCE
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HA
CE
R/W
ADDRESS
t
HZOE
OE
D
OUT
DATA
IN
Either Port
t
AW
t
WC
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HZWE
t
HA
HIGH IMPEDANCE
DATA VALID
t
LZWE
ADDRESS
CE
R/W
DATA
OUT
DATA
IN
Notes
36. The internal write time of the memory is defined by the overlap of CS
LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
37. If OE
is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or t
HZWE
+ t
SD
to allow the data I/O pins to enter high impedance
and for data to be placed on the bus for the required t
SD
.
38. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
39. If the CE
LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.

CY7C131-15NXI

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 8K PARALLEL 52PQFP
Lifecycle:
New from this manufacturer.
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