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CY7C131-15NXI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
CY7C130, CY7C130A
CY7C131, CY7C131A
Document Number: 38-06002 Rev. *H Page 7 of 22
Switching Characteristics
Over the Operating Range
[12, 13]
Parameter Description
7C131-15
[14]
7C131A-15
7C141-15
7C130-25
[14]
7C131-25
7C140-25
7C141-25
7C130-30
7C130A-30
7C131-30
7C140-30
7C141-30
Unit
Min Max Min Max Min Max
Read Cycle
t
RC
Read cycle time 15 –25–30–ns
t
AA
Address to data valid
[15]
– 15–25–30ns
t
OHA
Data hold from address change 0 –0–0–ns
t
ACE
CE LOW to data valid
[15]
– 15–25–30ns
t
DOE
OE LOW to data valid
[15]
– 10–15–20ns
t
LZOE
OE LOW to low Z
[16, 17, 18]
3 –3–3–ns
t
HZOE
OE HIGH to high Z
[16, 17, 18]
– 10–15–15ns
t
LZCE
CE LOW to low Z
[16, 17, 18]
3 –5–5–ns
t
HZCE
CE HIGH to high Z
[16, 17, 18]
– 10–15–15ns
t
PU
CE LOW to power-up
[16]
0 –0–0–ns
t
PD
CE HIGH to power-down
[16]
– 15–25–25ns
Write Cycle
[19]
t
WC
Write cycle time 15 –25–30–ns
t
SCE
CE LOW to write end 12 –20–25–ns
t
AW
Address setup to write end 12 –20–25–ns
t
HA
Address hold from write end 2 –2–2–ns
t
SA
Address setup to write start 0 –0–0–ns
t
PWE
R/W pulse width 12 –15–25–ns
t
SD
Data setup to write end 10 –15–15–ns
t
HD
Data hold from write end 0 –0–0–ns
t
HZWE
R/W LOW to high Z
[18]
– 10–15–15ns
t
LZWE
R/W HIGH to low Z
[18]
0 –0–0–ns
Shaded areas contain preliminary information.
Notes
12. See the last page of this specification for Group A subgroup testing information.
13. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V and output loading of the specified
I
OL
/I
OH,
and 30 pF load capacitance.
14. 15 and 25 ns version available only in PLCC/PQFP packages.
15. AC Test Conditions use V
OH
= 1.6 V and V
OL
= 1.4 V.
16. This parameter is guaranteed but not tested.
17. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
18. t
LZCE
, t
LZWE
, t
HZOE
, t
LZOE
, t
HZCE
and t
HZWE
are tested with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
19. The internal write time of the memory is defined by the overlap of CS
LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
CY7C130, CY7C130A
CY7C131, CY7C131A
Document Number: 38-06002 Rev. *H Page 8 of 22
Busy/Interrupt Timing
t
BLA
BUSY LOW from address match – 15–20–20ns
t
BHA
BUSY HIGH from address mismatch
[20]
– 15–20–20ns
t
BLC
BUSY LOW from CE LOW – 15–20–20ns
t
BHC
BUSY HIGH from CE HIGH
[20]
– 15–20–20ns
t
PS
Port set-up for priority 5 –5–5–ns
t
WB
[21]
R/W LOW after BUSY LOW 0 –0–0–ns
t
WH
R/W HIGH after BUSY HIGH 13 –20–30–ns
t
BDD
BUSY HIGH to valid data – 15–25–30ns
t
DDD
Write data valid to read data valid – Note 22 – Note 22 – Note 22 ns
t
WDD
Write pulse to data delay – Note 22 – Note 22 – Note 22 ns
Interrupt Timing
t
WINS
R/W to INTERRUPT set time – 15–25–25ns
t
EINS
CE to INTERRUPT set time – 15–25–25ns
t
INS
Address to INTERRUPT set time – 15–25–25ns
t
OINR
OE to INTERRUPT reset time
[20]
– 15–25–25ns
t
EINR
CE to INTERRUPT reset time
[20]
– 15–25–25ns
t
INR
Address to INTERRUPT reset time
[20]
– 15–25–25ns
Shaded areas contain preliminary information.
Switching Characteristics
Over the Operating Range
[12, 13]
(continued)
Parameter Description
7C131-15
[14]
7C131A-15
7C141-15
7C130-25
[14]
7C131-25
7C140-25
7C141-25
7C130-30
7C130A-30
7C131-30
7C140-30
7C141-30
Unit
Min Max Min Max Min Max
Notes
20. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
21. CY7C140/CY7C141 only.
22. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY
on Port B goes HIGH.
Port B’s address is toggled.
CE
for Port B is toggled.
R/W
for Port B is toggled during valid read.
CY7C130, CY7C130A
CY7C131, CY7C131A
Document Number: 38-06002 Rev. *H Page 9 of 22
Switching Characteristics
Over the Operating Range
[23, 24]
Parameter Description
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55
Unit
Min Max Min Max Min Max
Read Cycle
t
RC
Read cycle time 35 – 45 – 55 – ns
t
AA
Address to data valid
[25]
– 35 – 45–55ns
t
OHA
Data hold from address change 0 – 0 – 0 – ns
t
ACE
CE LOW to data valid
[25]
– 35 – 45–55ns
t
DOE
OE LOW to data valid
[25]
– 20 – 25–25ns
t
LZOE
OE LOW to low Z
[26, 27, 28]
3 – 3 –3–ns
t
HZOE
OE HIGH to high Z
[26, 27, 28]
– 20 – 20–25ns
t
LZCE
CE LOW to low Z
[26, 27, 28]
5 – 5 –5–ns
t
HZCE
CE HIGH to high Z
[26, 27, 28]
– 20 – 20–25ns
t
PU
CE LOW to power-up
[26]
0 – 0 –0–ns
t
PD
CE HIGH to power-down
[26]
– 35 – 35–35ns
Write Cycle
[29]
t
WC
Write cycle time 35 – 45 – 55 – ns
t
SCE
CE LOW to write end 30 – 35 – 40 – ns
t
AW
Address set-up to write end 30 – 35 – 40 – ns
t
HA
Address hold from write end 2 – 2 – 2 – ns
t
SA
Address set-up to write start 0 – 0 – 0 – ns
t
PWE
R/W pulse width 25 – 30 – 30 – ns
t
SD
Data set-up to write end 15 – 20 – 20 – ns
t
HD
Data hold from write end 0 – 0 – 0 – ns
t
HZWE
R/W LOW to high Z
[28]
– 20 – 20–25ns
t
LZWE
R/W HIGH to low Z
[28]
0 – 0 –0–ns
Notes
23. See the last page of this specification for Group A subgroup testing information.
24. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V and output loading of the specified
I
OL
/I
OH,
and 30 pF load capacitance.
25. AC Test Conditions use V
OH
= 1.6 V and V
OL
= 1.4 V.
26. This parameter is guaranteed but not tested.
27. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
28. t
LZCE
, t
LZWE
, t
HZOE
, t
LZOE
, t
HZCE
and t
HZWE
are tested with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
29. The internal write time of the memory is defined by the overlap of CS
LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
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CY7C131-15NXI

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Buy CY7C131-15NXI
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 8K PARALLEL 52PQFP
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