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CY7C131-15NXI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
CY7C130, CY7C130A
CY7C131, CY7C131A
Document Number: 38-06002 Rev. *H Page 13 of 22
Figure 10. Busy Timing Diagram No. 1 (CE Arbitration)
Figure 11. Busy Timing Diagram No. 2 (Address Arbitration)
Switching Waveforms (continued)
ADDRESS MATCH
t
PS
CE
L
Valid First:
t
BLC
t
BHC
ADDRESS MATCH
t
PS
t
BLC
t
BHC
ADDRESS
L,R
BUSY
R
CE
L
CE
R
BUSY
L
CE
R
CE
L
ADDRESS
L,R
CE
R
Valid First:
Left Address Valid First:
ADDRESS MATCH
t
PS
ADDRESS
L
BUSY
R
ADDRESS MISMATCH
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
ADDRESS MATCH ADDRESS MISMATCH
t
PS
ADDRESS
L
BUSY
L
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
Right Address Valid First:
CY7C130, CY7C130A
CY7C131, CY7C131A
Document Number: 38-06002 Rev. *H Page 14 of 22
Figure 12. Busy Timing Diagram No. 3
Switching Waveforms (continued)
t
PWE
t
WB
t
WH
Write with BUSY (Slave:CY7C140/CY7C141)
BUSY
R/W
CE
CY7C130, CY7C130A
CY7C131, CY7C131A
Document Number: 38-06002 Rev. *H Page 15 of 22
Figure 13. Interrupt Timing Diagrams
Switching Waveforms (continued)
WRITE 3FF
t
INS
t
WC
t
EINS
Right Side Clears INT
R
t
HA
t
SA
t
WINS
READ 3FF
t
RC
t
EINR
t
HA
t
INT
t
OINR
WRITE 3FE
t
INS
t
WC
t
EINS
t
HA
t
SA
t
WINS
Right Side Sets INT
L
Left Side Sets INT
R
Left Side Clears INT
L
READ 3FE
t
EINR
t
HA
t
INR
t
OINR
t
RC
ADDR
R
CE
L
R/W
L
INT
L
OE
L
ADDR
R
R/W
R
CE
R
INT
L
ADDR
R
CE
R
R/W
R
INT
R
OE
R
ADDR
L
R/W
L
CE
L
INT
R
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

CY7C131-15NXI

Mfr. #:
Buy CY7C131-15NXI
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 8K PARALLEL 52PQFP
Lifecycle:
New from this manufacturer.
Delivery:
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