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M48T512V-85PM1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
Operating modes M48T512Y, M48T512V
10/23 Doc ID 5747 Rev 7
Table 4. WRITE mode AC characteristics
2.3 Data retention mode
With valid V
CC
applied, the M48T512Y/V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting
itself when V
CC
falls between V
PFD
(max) and V
PFD
(min). All outputs become high
impedance and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may corrupt data at the current addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
PFD
(min), the
memory will be in a write protected state, provided the V
CC
fall time is not less than t
F
. The
M48T512Y/V may respond to transient noise spikes on V
CC
that cross into the deselect
window during the time the device is sampling V
CC
.Therefore, decoupling of the power
supply lines is recommended. When V
CC
drops below V
SO
, the control circuit switches
power to the internal battery, preserving data and powering the clock. The internal energy
source will maintain data in the M48T512Y/V for an accumulated period of at least 10 years
at room temperature. As system power rises above V
SO
, the battery is disconnected, and
the power supply is switched to external V
CC
. Write protection continues until V
CC
reaches
V
PFD
(min) plus t
REC
(min). Normal RAM operation can resume t
REC
after V
CC
exceeds
V
PFD
(max). Refer to application note (AN1012) on the ST website for more information on
battery life.
Symbol Parameter
(1)
1. Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
M48T512Y M48T512V
Unit-70 -85
Min Max Min Max
t
AVAV
WRITE cycle time 70 85 ns
t
AVWL
Address valid to WRITE enable low 0 0 ns
t
AVEL
Address valid to chip enable low 0 0 ns
t
WLWH
WRITE enable pulse width 50 60 ns
t
ELEH
Chip enable low to chip enable high 55 65 ns
t
WHAX
WRITE enable high to address transition 5 5 ns
t
EHAX
Chip enable high to address transition 10 15 ns
t
DVWH
Input valid to WRITE enable high 30 35 ns
t
DVEH
Input valid to chip enable high 30 35 ns
t
WHDX
WRITE enable high to input transition 5 5 ns
t
EHDX
Chip enable high to input transition 10 15 ns
t
WLQZ
(2)(3)
2. C
L
= 5pF.
3. If E
goes low simultaneously with W going low, the outputs remain in the high impedance state.
WRITE enable low to output Hi-Z 25 30 ns
t
AVWH
Address valid to write enable high 60 70 ns
t
AVEH
Address valid to chip enable high 60 70 ns
t
WHQX
(2)(3)
WRITE enable high to output transition 5 5 ns
Obsolete Product(s) - Obsolete Product(s)
M48T512Y, M48T512V Clock operations
Doc ID 5747 Rev 7 11/23
3 Clock operations
3.1 Reading the clock
Updates to the TIMEKEEPER
®
registers should be halted before clock data is read to
prevent reading data in transition (see Table 5 on page 12). The BiPORT™ TIMEKEEPER
cells in the RAM array are only data registers and not the actual clock counters, so updating
the registers can be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, D6 in the control register (7FFF8h).
As long as a '1' remains in that position, updating is halted. After a halt is issued, the
registers reflect the count; that is, the day, date, and time that were current at the moment
the halt command was issued. All of the TIMEKEEPER registers are updated
simultaneously. A halt will not interrupt an update in progress. The next update occurs 1
second after the READ bit is reset to a '0.'
3.2 Setting the clock
Bit D7 of the control register (7FFF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like
the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them
with the correct day, date, and time data in 24 hour BCD format (see Table 5 on page 12).
Resetting the WRITE bit to a '0' then transfers the values of all time registers 7FFFFh-
7FFF9h to the actual TIMEKEEPER counters and allows normal operation to resume. After
the WRITE bit is reset, the next clock update will occur approximately one second later.
Note: Upon power-up, both the WRITE bit and the READ bit will be reset to '0.'
3.3 Stopping and starting the oscillator.
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP bit is located at bit D7 within 7FFF9h. Setting it to a '1' stops the
oscillator. The M48T512Y/V is shipped from STMicroelectronics with the STOP bit set to a
'1.' When reset to a '0,' the M48T512Y/V oscillator starts after approximately one second.
Note: It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).
Obsolete Product(s) - Obsolete Product(s)
Clock operations M48T512Y, M48T512V
12/23 Doc ID 5747 Rev 7
Table 5. Register map
Keys:
S = SIGN bit
R = READ bit
W = WRITE bit
ST = STOP bit
0 = Must be set to '0'
3.4 Calibrating the clock
The M48T512Y/V is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are factory calibrated at 25 °C and tested for accuracy. Clock
accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25 °C, which
equates to about ±1.53 minutes per month. When the Calibration circuit is properly
employed, accuracy improves to better than +1/–2 ppm at 25 °C. The oscillation rate of
crystals changes with temperature. The M48T512Y/V design employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 256 stage (see Figure 8 on page 13).
The number of times pulses are blanked (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five calibration bits found in the
control register. Adding counts speeds the clock up, subtracting counts slows the clock
down. The calibration bits occupy the five lower order bits (D4-D0) in the control register
7FFF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit
D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration
occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step
has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120
actual oscillator cycles; that is, +4.068 or –2.034 ppm of adjustment per calibration step in
the calibration register.
Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in
the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds
to a total range of +5.5 or –2.75 minutes per month.
Address
Data
Function/range
BCD format
D7 D6 D5 D4 D3 D2 D1 D0
7FFFFh 10 years Year Year 00-99
7FFFEh 0 0 0 10 M Month Month 01-12
7FFFDh 0 0 10 date Date Date 01-31
7FFFCh 0 0 0 0 0 Day Day 01-07
7FFFBh 0 0 10 hours Hours Hours 00-23
7FFFAh 0 10 minutes Minutes Minutes 00-59
7FFF9h ST 10 seconds Seconds Seconds 00-59
7FFF8h W R S Calibration Control
Obsolete Product(s) - Obsolete Product(s)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

M48T512V-85PM1

Mfr. #:
Buy M48T512V-85PM1
Manufacturer:
STMicroelectronics
Description:
Real Time Clock 4 MBIT 512 Kbitx8 TIMEKEEPER
Lifecycle:
New from this manufacturer.
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