M48T512Y, M48T512V Operating modes
Doc ID 5747 Rev 7 7/23
2 Operating modes
The 32-pin, 600 mil hybrid DIP houses a controller chip, SRAM, quartz crystal, and a long
life lithium button cell in a single package. Figure 3 on page 6 illustrates the static memory
array and the quartz controlled clock oscillator. The clock locations contain the year, month,
date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year
- compliant until the year 2100), 30, and 31 day months are made automatically. Byte
7FFF8h is the clock control register (see Table 5 on page 12). This byte controls user
access to the clock information and also stores the clock calibration setting. The seven clock
bytes (7FFFFh-7FFF9h) are not the actual clock counters; they are memory locations
consisting of BiPORT™ READ/WRITE memory cells within the static RAM array. The
M48T512Y/V includes a clock control circuit which updates the clock bytes with current
information once per second. The information can be accessed by the user in the same
manner as any other location in the static memory array. The M48T512Y/V also has its own
power-fail detect circuit. This control circuitry constantly monitors the supply voltage for an
out of tolerance condition. When V
CC
is out of tolerance, the circuit write protects the
TIMEKEEPER register data and SRAM, providing data security in the midst of unpredictable
system operation. As V
CC
falls, the control circuitry automatically switches to the battery,
maintaining data and clock operation until valid power is restored.
Table 2. Operating modes
Note: X = V
IH
or V
IL
; V
SO
= Battery backup switchover voltage.
2.1 READ mode
The M48T512Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The unique address specified by the 19 address inputs defines which one of
the 524,288 bytes of data is to be accessed. Valid data will be available at the data I/O pins
within address access time (t
AVQV
) after the last address input signal is stable, providing the
E
and G access times are also satisfied. If the E and G access times are not met, valid data
will be available after the latter of the chip enable access times (t
ELQV
) or output enable
access time (t
GLQV
). The state of the eight three-state data I/O signals is controlled by E and
G
. If the outputs are activated before t
AVQV
, the data lines will be driven to an indeterminate
state until t
AVQV
. If the address inputs are changed while E and G remain active, output data
will remain valid for output data hold time (t
AXQX
) but will go indeterminate until the next
address access.
Mode V
CC
E G W DQ0-DQ7 Power
Deselect
4.5 to 5.5 V
or
3.0 to 3.6 V
V
IH
X X High Z Standby
WRITE V
IL
XV
IL
D
IN
Active
READ V
IL
V
IL
V
IH
D
OUT
Active
READ V
IL
V
IH
V
IH
High Z Active
Deselect V
SO
to V
PFD
(min)
(1)
1. See Table 11 on page 18 for details.
X X X High Z CMOS standby
Deselect ≤ V
SO
(1)
X X X High Z Battery backup mode
Obsolete Product(s) - Obsolete Product(s)
