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SC28L91A1B,557

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43
Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21
13
UnitMaxTypMinParameterSymbol
Receiver Timing, external clock (See Figure 13)
t
*RXS
RxD data setup time to RxC high 50 40 ns
t
*RXH
RxD data hold time from RxC high 50 40 ns
68000 or Motorola bus timing (See Figures 6, 7, 8)
10
t
DCR
DACKN Low (read cycle) from X1 High
10
15 35 ns
t
DCW
DACKN Low (write cycle) from X1 High 15 35 ns
t
DAT
DACKN High impedance from CEN or IACKN High 8 10 ns
t
CSC
CEN or IACKN setup time to X1 High for minimum DACKN cycle 16 ns
NOTES:
1. Parameters are valid over specified temperature and voltage range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of
5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8*V
CC
. All time measurements are referenced at input voltages of 0.8 V and
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.
3. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: C
L
= 125 pF,
constant current source = 2.6 mA.
4. Typical values are the average values at +25 °C and 5 V.
5. Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the “strobing” input. CEN and RDN (also CEN and
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.
6. Guaranteed by characterization of sample units.
7. If CEN is used as the “strobing” input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for t
RWD
to guarantee that any status register changes are valid.
8. Minimum frequencies are not tested but are guaranteed by design.
9. Clocks for 1X mode should maintain a 60/40 duty cycle or better.
10.Minimum DACKN time is t
DCR
= t
DSC
+ t
DCR
+ two positive edges of the X1 clock. For faster bus cycles, the 80XXX bus timing may be used
while in the 68XXX mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C91. In all cases the data will be
written to the SC28L91 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the
bus cycle. DACKN low or CEN high completes the write cycle.
0 20 40 60 80 100 120 140 160 180 200 220 240
60
55
50
45
40
35
30
25
20
15
10
5
0
V
CC
= 3.3 V @ +25 °C
5.0 V @ +25 °C
pF
T
dd
(ns)
125 pF30 pF 230 pF
SD00684
12 pF 100 pF
NOTES:
Bus cycle times:
(80XXX mode): t
DD
+ t
RWD
= 70 ns @ 5V, 40 ns @ 3.3 V + rise and fall time of control signals
(68XXX mode) = t
CSC
+ t
DAT
+ 1 cycle of the X1 clock @ 5 V + rise and fall time of control signals
Figure 3. Port Timing vs. Capacitive Loading at typical conditions
Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21
14
AC CHARACTERISTICS (3.3 VOLT)
1,
2,
3,
4
V
CC
= 3.3 V ± 10 %, T
amb
= –40 °C to +85 °C, unless otherwise specified.
Symbol Parameter Min Typ Max Unit
Reset Timing (See Figure 4)
t
RES
Reset pulse width 100 20 ns
Bus Timing
5
(See Figure 5)
t
*AS
A0–A3 setup time to RDN, WRN Low 10 6 ns
t
*AH
A0–A3 hold time from RDN, WRN low 33 ns
t
*CS
CEN setup time to RDN, WRN low 0 ns
t
*CH
CEN Hold time from RDN. WRN low 0 ns
t
*RW
WRN, RDN pulse width (Low time) 20 10 ns
t
*DD
Data valid after RDN low (125pF load. See Figure 3 for smaller loads.) 46 75 ns
t
*DA
RDN low to data bus active
6
0 ns
t
*DF
Data bus floating after RDN or CEN high 15 20 ns
t
*DI
RDN or CEN high to data bus invalid
7
0 ns
t
*DS
Data bus setup time before WRN or CEN high (write cycle) 43 ns
t
*DH
Data hold time after WRN high 0 –15 ns
t
*RWD
High time between read and/or write cycles
5,
7
27 ns
Port Timing
5
(See Figure 9)
t
*PS
Port in setup time before RDN low (Read IP ports cycle) 0 –20 ns
t
*PH
Port in hold time after RDN high 0 –20 ns
t
*PD
OP port valid after WRN or CEN high (OPR write cycle) 50 75 ns
Interrupt Timing (See Figure 10)
t
*IR
INTRN (or OP3–OP7 when used as interrupts) negated from:
Read RxFIFO (RxRDY/FFULL interrupt) 40 79 ns
Write TxFIFO (TxRDY interrupt) 40 79 ns
Reset Command (delta break change interrupt) 40 79 ns
Stop C/T command (Counter/timer interrupt) 40 79 ns
Read IPCR (delta input port change interrupt) 40 79 ns
Write IMR (Clear of change interrupt mask bit(s)) 40 79 ns
Clock Timing (See Figure 11)
t
*CLK
X1/CLK high or low time 35 25 ns
f
*CLK
X1/CLK frequency
8
(for higher speeds contact factory) 0.1 3.686 8 MHz
f
*CTC
C/T Clk (IP2) high or low time (C/T external clock input) 30 15 ns
f
*CTC
C/T Clk (IP2) frequency
8
(for higher speeds contact factory) 0 8 MHz
t
*RX
RxC high or low time (16X) 30 10 ns
f
*RX
RxC Frequency (16X) (for higher speeds contact factory) 0 16 MHz
RxC Frequency (1x)
8,
9
0 1 MHz
t
*TX
TxC High or low time (16X) 30 15 ns
f
*TX
TxC frequency (16X) (for higher speeds contact factory) 16 MHz
TxC frequency (1X)
8,
9
0 1 MHz
Transmitter Timing, external clock (See Figure 12)
t
*TXD
TxD output delay from TxC low (TxC input pin) 40 78 ns
t
*TCS
Output delay from TxC output pin low to TxD data output 8 30 ns
Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21
15
UnitMaxTypMinParameterSymbol
Receiver Timing, external clock (See Figure 13)
t
*RXS
RxD data setup time to RxC high 50 10 ns
t
*RXH
RxD data hold time from RxC high 50 10 ns
68000 or Motorola bus timing (See Figures 6, 7, 8)
10
t
DCR
DACKN Low (read cycle) from X1 High
10
18 57 ns
t
DCW
DACKN Low (write cycle) from X1 High 18 57 ns
t
DAT
DACKN High impedance from CEN or IACKN High 10 15 ns
t
CSC
CEN or IACKN setup time to X1 High for minimum DACKN cycle 30 10 ns
NOTES:
1. Parameters are valid over specified temperature and voltage range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of
5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8*V
CC
. All time measurements are referenced at input voltages of 0.8 V and
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.
3. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: C
L
= 125 pF,
constant current source = 2.6 mA.
4. Typical values are the average values at +25 °C and 3.3 V.
5. Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the “strobing” input. CEN and RDN (also CEN and
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.
6. Guaranteed by characterization of sample units.
7. If CEN is used as the “strobing” input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for t
RWD
to guarantee that any status register changes are valid.
8. Minimum frequencies are not tested but are guaranteed by design.
9. Clocks for 1X mode should maintain a 60/40 duty cycle or better.
10.Minimum DACKN time is t
DCR
= t
DSC
+ t
DCR
+ two positive edges of the X1 clock. For faster bus cycles, the 80XXX bus timing may be used
while in the 68XXX mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C91. In all cases the data will be
written to the SC28L91 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the
bus cycle. DACKN low or CEN high completes the write cycle.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43

SC28L91A1B,557

Mfr. #:
Buy SC28L91A1B,557
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 3V-5V 1CH UART INTEL/MOT INTRF
Lifecycle:
New from this manufacturer.
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