SC28L91A1B,557 Datasheet SC28L91A1B,528, SC28L91A1B,557, SC28L91A1B,551 | P16-P18

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21

Block Diagram

The SC28L91 UART consists of the following seven major sections:

data bus buffer, operation control, interrupt control, timing, Rx and

Tx FIFO Buffers, input port and output port control. Refer to the

Block Diagram.

Data Bus Buffer

The data bus buffer provides the interface between the external and

internal data buses. It is controlled by the operation control block to

allow read and write operations to take place between the controlling

CPU and the UART.

Operation Control

The operation control logic receives operation commands from the

CPU and generates appropriate signals to internal sections to

control device operation. It contains address decoding and read and

write circuits to permit communications with the microprocessor via

the data bus.

Interrupt Control

A single active-Low interrupt output (INTRN) is provided which is

activated upon the occurrence of any of eight internal events.

Associated with the interrupt system are the Interrupt Mask Register

(IMR) and the Interrupt Status Register (ISR). The IMR can be

programmed to select only certain conditions to cause INTRN to be

asserted. The ISR can be read by the CPU to determine all currently

active interrupting conditions. Outputs OP3–OP7 can be

programmed to provide discrete interrupt outputs for the transmitter,

receiver, and counter/timer. Programming the OP3 to OP7 pins as

interrupts causes their output buffers to change to an open drain

active low configuration. The OP pins may be used for DMA and

modem control as well. (See output port notes).

FIFO Configuration

Each receiver and transmitter has a 16 byte FIFO. These FIFOs

may be configured to operate at a fill capacity of either 8 or 16 bytes.

This feature may be used if it is desired to operate the 28L91 in

close compliance to 26C92 software. The 8-byte/16-byte mode is

controlled by the MR0[3] bit. A 0 value for this bit sets the 8-bit mode

( the default); a 1 sets the 16-byte mode.

The FIFO fill interrupt level automatically follow the programming of

the MR0[3] bit. See Tables 3 and 4.

68XXX mode

When the I/M pin is connected to V

(ground), the operation of the

SC28L91 switches to the bus interface compatible with the Motorola

bus interfaces. Several of the pins change their function as follows:

• IP6 becomes IACKN input

• RDN becomes DACKN

• WRN becomes R/WN

The interrupt vector is enabled and the interrupt vector will be placed

on the data bus when IACKN is asserted low. The interrupt vector

set to 0x0F on the application of RESETN.

The generation of DACKN uses two positive edges of the X1 clock

as the DACKN delay from the falling edge of CEN. If the CEN is

withdrawn before two edges of the X1 clock occur, the

generation of DACKN is terminated. Systems not strictly requiring

DACKN may use the 68XXX mode with the bus timing of the 80XXX

mode greatly decreasing the bus cycle time.

TIMING CIRCUITS

Crystal Clock

The timing block consists of a crystal oscillator, a baud rate

generator, a programmable 16-bit counter/timer, and four clock

selectors. The crystal oscillator operates directly from a crystal

connected across the X1/CLK and X2 inputs. If an external clock of

the appropriate frequency is available, it may be connected to

X1/CLK. The clock serves as the basic timing reference for the Baud

Rate Generator (BRG), the counter/timer, and other internal circuits.

A clock signal within the limits specified in the specifications section

of this data sheet must always be supplied to the UART. If an

external clock is used instead of a crystal, X1 should be driven using

a configuration similar to the one in Figure 11. X2 should be open or

driving a nominal gate load. Nominal crystal rate is 3.6864 MHz.

Rates up to 8 MHz may be used.

BRG

The baud rate generator operates from the oscillator or external

clock input and is capable of generating 28 commonly used data

communications baud rates ranging from 50 to 38.4 K baud.

Programming bit 0 of MR0 to a “1” gives additional baud rates of

57.6 kB, 115.2 kB and 230.4 kB (500 kHz with X1 at 8.0 MHz).

These will be in the 16X mode. A 3.6864 MHz crystal or external

clock must be used to get the standard baud rates. The clock

outputs from the BRG are at 16X the actual baud rate. The

counter/timer can be used as a timer to produce a 16X clock for any

other baud rate by counting down the crystal clock or an external

clock. The four clock selectors allow the independent selection, for

the receiver and transmitter, of any of these baud rates or external

timing signal.

Counter/Timer

The counter timer is a 16-bit programmable divider that operates in

one of three modes: counter, timer, and time out. In the timer mode it

generates a square wave. In the counter mode it generates a time

delay. In the time out mode it monitors the time between received

characters. The C/T uses the numbers loaded into the

Counter/Timer Lower Register (CTLR) and the Counter/Timer Upper

The counter/timer clock source and mode of operation (counter or

timer) is selected by the Auxiliary Control Register bits 6 to 4

(ACR[6:4]). The output of the counter/timer may be used for a baud

rate and/or may be output to the OP pins for some external function

that may be totally unrelated to data transmission. The counter/timer

also sets the counter/timer ready bit in the Interrupt Status Register

(ISR) when its output transitions from 1 to 0. A register read address

(see Table 1) is reserved to issue a start counter/timer command

and a second register read address is reserved to issue a stop

command. The value of D[7:0] is ignored. The START command

always loads the contents of CTUR, CTLR to the counting registers.

The STOP command always resets the ISR[3] bit in the interrupt

status register.

Timer Mode

In the timer mode a symmetrical square wave is generated whose

half period is equal in time to division of the selected counter/timer

clock frequency by the 16-bit number loaded in the CTLR CTUR.

Thus, the frequency of the counter/timer output will be equal to the

counter/timer clock frequency divided by twice the value of the

CTUR CTLR. While in the timer mode the ISR bit 3 (ISR[3]) will be

set each time the counter/timer transitions from 1 to 0. (High to low)

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21

This continues regardless of issuance of the stop counter command.

ISR[3] is reset by the stop counter command.

NOTE: Reading of the CTU and CTL registers in the timer mode is

not meaningful. When the C/T is used to generate a baud rate and

the C/T is selected through the CSR then the receiver and/or

transmitter will be operating in the 16x mode. Calculation for the

number ‘n’ to program the counter timer upper and lower registers is

shown below.

N +

cńtclockrate

2 * 16 * Baud rate

Often this division will result in a non-integer number; 26.3 for

example. One can only program integer numbers to a digital divider.

Therefore 26 would be chosen. This gives a baud rate error of

0.3/26.3 which is 1.14%; well within the ability of the asynchronous

mode of operation.

Counter Mode

In the counter mode the counter/timer counts the value of the CTLR

CTUR down to zero and then sets the ISR[3] bit and sets the

counter/timer output from 1 to 0. It then rolls over to 65,365 and

continues counting with no further observable effect. Reading the

C/T in the counter mode outputs the present state of the C/T. If the

C/T is not stopped, a read of the C/T may result in changing data on

the data bus.

Timeout Mode

The timeout mode uses the received data stream to control the

counter. The time-out mode forces the C/T into the timer mode.

Each time a received character is transferred from the shift register

to the RxFIFO, the counter is restarted. If a new character is not

received before the counter reaches zero count, the counter ready

bit is set, and an interrupt can be generated. This mode can be used

to indicate when data has been left in the Rx FIFO for more than the

programmed time limit. If the receiver has been programmed to

interrupt the CPU when the receive FIFO is full, and the message

ends before the FIFO is full, the CPU will not be interrupted for the

remaining characters in the RxFIFO.

By programming the C/T such that it would time out in just over one

character time, the above situation could be avoided. The processor

would be interrupted any time the data stream had stopped for more

than one character time. NOTE: This is very similar to the watch dog

timer of MR0. The difference is in the programmability of the delay

timer and that this indicates that the data stream has stopped. The

watchdog timer is more of an indicator that data is in the FIFO is not

enough to cause an interrupt. The watchdog is restarted by either a

receiver load to the RxFIFO or a system read from it.

This mode is enabled by writing the appropriate command to the

command register. Writing an ‘0xAn’ to CR will invoke the timeout

mode for that channel. Writing a ‘Cx’ to CR will disable the timeout

mode. The timeout mode disables the regular START/STOP counter

commands and puts the C/T into counter mode under the control of

the received data stream. Each time a received character is

transferred from the shift register to the RxFIFO, the C/T is stopped

after one C/T clock, reloaded with the value in CTUR and CTLR and

then restarted on the next C/T clock. If the C/T is allowed to end the

count before a new character has been received, the counter ready

Bit, ISR[3], will be set. If IMR[3] is set, this will generate an interrupt.

Since receiving a character restarts the C/T, the receipt of a

character after the C/T has timed out will clear the counter ready bit,

ISR [3], and the interrupt. Invoking the ‘Set Timeout Mode On’

command, CRx = 0xAn, will also clear the counter ready bit and stop

the counter until the next character is received. The counter timer is

controlled with six commands: Start/Stop C/T, Read/Write

Counter/Timer lower register and Read/Write Counter/Timer upper

mode of operation. Please see the detail of the commands under the

CTLR CTUR Register descriptions.

Time Out Mode Caution

When operating in the special time out mode it is possible to

generate what appears to be a “false interrupt”, i.e. an interrupt

without a cause. This may result when a time-out interrupt occurs

and then, BEFORE the interrupt is serviced, another character is

received, i.e., the data stream has started again. (The interrupt

latency is longer than the pause in the data stream.) In this case,

when a new character has been receiver, the counter/timer will be

restarted by the receiver, thereby withdrawing its interrupt. If, at this

time, the interrupt service begins for the previously seen interrupt, a

read of the ISR will show the “Counter Ready” bit not set. If nothing

else is interrupting, this read of the ISR will return a x’00 character.

This action may present the appearance of a spurious interrupt.

Communications

The communications channel of the SC28L91 comprises a

full-duplex asynchronous receiver/transmitter (UART). The operating

frequency for the receiver and transmitter can be selected

independently from the baud rate generator, the counter/timer, or

from an external input. The transmitter accepts parallel data from the

CPU, converts it to a serial bit stream, inserts the appropriate start,

stop, and optional parity bits and outputs a composite serial stream

of data on the TxD output pin. The receiver accepts serial data on

the RxD pin, converts this serial input to parallel format, checks for

start bit, stop bit, parity bit (if any), or break condition and sends an

assembled character to the CPU via the receive FIFO. Three status

bits (Break Received, Framing and Parity Errors) are also FIFOed

with the data character.

Input Port

The inputs to this unlatched 7-bit (6-bit for 68xxx mode) port can be

read by the CPU by performing a read operation at address 0xD. A

High input results in a logic 1 while a Low input results in a logic 0.

D7 will always read as a logic 1. The pins of this port can also serve

as auxiliary inputs to certain portions of the UART logic, modem and

DMA.

Four change-of-state detectors are provided which are associated

with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High

transition of these inputs, lasting longer than 25–50 µs, will set the

corresponding bit in the input port change register. The bits are

cleared when the register is read by the CPU. Any change-of-state

can also be programmed to generate an interrupt to the CPU.

The input port change of state detection circuitry uses a 38.4 kHz

sampling clock derived from one of the baud rate generator taps.

This results in a sampling period of slightly more than 25 µs (this

assumes that the clock input is 3.6864 MHz). The detection circuitry,

in order to guarantee that a true change in level has occurred,

requires two successive samples at the new logic level be observed.

As a consequence, the minimum duration of the signal change is

25 µs if the transition occurs “coincident with the first sample pulse”.

The 50 µs time refers to the situation in which the change-of-state is

Philips Semiconductors Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous

Receiver/Transmitter (UART)

2004 Oct 21

“just missed” and the first change-of-state is not detected until 25 µs

later.

Output Port

The output ports are controlled from six places: the OPCR, OPR,

MR, Command, SOPR and ROPR registers. The OPCR register

controls the source of the data for the output ports OP2 through

OP7. The data source for output ports OP0 and OP1 is controlled by

the MR and CR registers. When the OPR is the source of the data

for the output ports, the data at the ports is inverted from that in the

OPR register. The content of the OPR register is controlled by the

“Set Output Port Bits Command” and the “Reset Output Bits

Command”. These commands are at E and F, respectively. When

these commands are used, action takes place only at the bit

locations where ones exist. For example, a one in bit location 5 of

the data word used with the “Set Output Port bits” command will

result in OPR[5] being set to one. The OP5 would then be set to

zero (V

). Similarly, a one in bit position 5 of the data word

associated with the “Reset Output Ports Bits” command would set

OPR[5] to zero and, hence, the pin OP5 to a one (V

These pins along with the IP pins and their change of state detectors

are often used for modem and DMA control.

OPERATION

Transmitter

The SC28L91 is conditioned to transmit data when the transmitter is

enabled through the command register. The SC28L91 indicates to

the CPU that it is ready to accept a character by setting the TxRDY

bit in the status register. This condition can be programmed to

generate an interrupt request at OP6 or OP7 and INTRN. When the

transmitter is initially enabled the TxRDY and TxEMPT bits will be

set in the status register. When a character is loaded to the transmit

FIFO the TxEMPT bit will be reset. The TxEMPT will not set until: 1)

the transmit FIFO is empty and the transmit shift register has

finished transmitting the stop bit of the last character written to the

transmit FIFO, or 2) the transmitter is disabled and then re-enabled.

The TxRDY bit is set whenever the transmitter is enabled and the

TxFIFO is not full. Data is transferred from the holding register to

transmit shift register when it is idle or has completed transmission

of the previous character. Characters cannot be loaded into the

TxFIFO while the transmitter is disabled.

The transmitter converts the parallel data from the CPU to a serial

bit stream on the TxD output pin. It automatically sends a start bit

followed by the programmed number of data bits, an optional parity

bit, and the programmed number of stop bits. The least significant

bit is sent first. Following the transmission of the stop bits, if a new

character is not available in the TxFIFO, the TxD output remains

High and the TxEMT bit in the Status Register (SR) will be set to 1.

Transmission resumes and the TxEMT bit is cleared when the CPU

loads a new character into the TxFIFO.

If the transmitter is disabled it continues operating until the character

currently being transmitted and any characters in the TxFIFO,

including parity and stop bits, have been transmitted. New data

cannot be loaded to the TxFIFO when the transmitter is disabled.

When the transmitter is reset it stops sending data immediately.

The transmitter can be forced to send a break (a continuous low

condition) by issuing a START BREAK command via the CR

transmitter reset.

If CTS option is enabled (MR2[4] = 1), the CTS input at IP0 or IP1

must be Low in order for the character to be transmitted. The

transmitter will check the state of the CTS input at the beginning of

the character transmitted. If it is found to be High, the transmitter will

delay the transmission of any following characters until the CTS has

returned to the low state. CTS going high during the serialization of

a character will not affect that character.

The transmitter can also control the RTSN outputs, OP0 or OP1 via

MR2[5]. When this mode of operation is set, the meaning of the OP0

or OP1 signals will usually be ‘end of message’. See description of

the MR2[5] bit for more detail. This feature may be used to

automatically “turn around” a transceiver in simplex systems.

Receiver

The SC28L91 is conditioned to receive data when enabled through

the command register. The receiver looks for a High-to-Low

(mark-to-space) transition of the start bit on the RxD input pin. If a

transition is detected, the state of the RxD pin is sampled the 16X

clock for 7–1/2 clocks (16X clock mode) or at the next rising edge of

the bit time clock (1X clock mode). If RxD is sampled high, the start

bit is invalid and the search for a valid start bit begins again. If RxD

is still Low, a valid start bit is assumed and the receiver continues to

sample the input at one-bit time intervals at the theoretical center of

the bit. When the proper number of data bits and parity bit (if any)

have been assembled, and one/half stop bit has been detected the

byte is loaded to the RxFIFO. The least significant bit is received

first. The data is then transferred to the Receive FIFO and the

RxRDY bit in the SR is set to a 1. This condition can be

programmed to generate an interrupt at OP4 or OP5 and INTRN. If

the character length is less than 8 bits, the most significant unused

bits in the RxFIFO are set to zero.

After the stop bit is detected, the receiver will immediately look for

the next start bit. However if a framing error occurs (a non-zero

character was received without a stop bit) and then RxD remains

low one/half bit time the receiver operates as if a new start bit was

detected. It then continues to assemble the next character.

The parity error, framing error, and overrun error (if any) are strobed

into the SR from the next byte to be read from the Rx FIFO.

If a break condition is detected (RxD is Low for the entire character

including the stop bit), a character consisting of all zeros will be

loaded into the RxFIFO and the received break bit in the SR is set to

1. The RxD input must return to high for two (2) clock edges of the

X1 crystal clock for the receiver to recognize the end of the break

condition and begin the search for a start bit.

This will usually require a high time of one X1 clock period or 3 X1

edges since the clock of the controller is not synchronous to the X1

clock.

Transmitter Reset and Disable

Note the difference between transmitter disable and reset. A

transmitter reset stops transmitter action immediately, clears the

transmitter FIFO and returns the idle state. A transmitter disable

withdraws the transmitter interrupts but allows the transmitter to

continue operation until all bytes in its FIFO and shift register have

been transmitted including the final stop bits. It then returns to its

idle state.

Receiver FIFO

The RxFIFO consists of a First-In-First-Out (FIFO) stack with a

capacity of 8 or 16 characters. Data is loaded from the receive shift

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P43

SC28L91A1B,557

Mfr. #:

Buy SC28L91A1B,557

Manufacturer:

NXP Semiconductors

Description:

UART Interface IC 3V-5V 1CH UART INTEL/MOT INTRF

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