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CPC7582MCTR

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CPC7582
R05 www.clare.com 13
Table” on page 10 and “CPC7582xC Truth Table” on
page 11.
2.2.1 Make-Before-Break Operation - All Versions
To use make-before-break operation, change the logic
inputs to the talk state immediately following the
ringing state. Application of the talk state opens the
ringing return switch (SW3) as the break switches
(SW1 and SW2) close. The ringing switch (SW4)
remains closed until the next zero-crossing of the
ringing supply current. While in the make-before-break
state, ringing potentials in excess of the CPC7582
protection circuitry trigger levels will be diverted to
ground.
2.2.2 Make-Before-Break Operation for All Versions (Ringing to Talk Transition)
2.2.3 Break-Before-Make Operation - CPC7582xA/B
Break-before-make operation of the CPC7582xA/B
can be achieved using two different techniques.
The first method uses manipulation of the IN
RINGING
and IN
TEST
logic inputs as shown in
“Break-Before-Make Operation CPC7582xA/B
(Ringing to Talk Transition)” on page 13.
1. At the end of the ringing state apply the all off
state (0, 0). This releases the ringing return
switch (SW3) while the ringing switch remains
on, waiting for the next zero current event.
2. Hold the all off state for at least one-half of a
ringing cycle to assure that a zero crossing event
occurs and that the ringing switch (SW4) has
opened.
Break-before-make operation occurs when the ringing
switch opens before the break switches (SW1 and
SW2) close.
2.2.4 Break-Before-Make Operation CPC7582xA/B (Ringing to Talk Transition)
2.2.5 Break-Before-Make Operation - All Versions
The second break-before-make method for the
CPC7582xA/B is also the only method available for
the CPC7582xC. As shown in “CPC7582xA/B Truth
Table” on page 10 and “CPC7582xC Truth Table” on
page 11, the bidirectional T
SD
interface disables all of
State
IN
RINGING
IN
TEST
LATCH
T
SD
Timing
Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
Ringing 1 0
0 Floating
-Off
On On Off
Make-
before-
break
00
SW4 waiting for next zero-current
crossing to turn off. Maximum time is
one-half of the ringing cycle. In this
transition state, current that is limited to
the dc break switch current limit value
will be sourced from the ring node of the
SLIC.
On Off On Off
Talk 0 0 Zero-cross current has occurred
On Off Off Off
State
IN
RINGING
IN
TEST
LATCH
T
SD
Timing
Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
Ringing 1 0
0 Floating
-Off
On On Off
All-Off 1 1
Hold this state for at least one-half of the
ringing cycle. SW4 waiting for zero
current to turn off.
Off Off
On Off
Break-
Before-
Make
1 1 SW4 has opened Off Off Off Off
Talk 0 0 Close Break Switches
On Off Off Off
CPC7582
14 www.clare.com R05
the CPC7582 switches when pulled to a logic low.
Although logically disabled, if the ringing switch (SW4)
is active (closed), it will remain closed until the next
current zero crossing event.
As shown in the table “Break-Before-Make Operation
for all Version (Ringing to Talk Transition)” on page 14,
this operation is similar to the one shown in
“Break-Before-Make Operation - All Versions” on
page 13, except in the method used to select the all off
state, and in when the IN
RINGING
and IN
TEST
inputs
are reconfigured for the talk state.
1. Pull T
SD
to a logic low to end the ringing state.
This opens the ringing return switch (SW3) and
prevents any other switches from closing.
2. Keep T
SD
low for at least one-half the duration of
the ringing cycle period to allow sufficient time for
a zero crossing current event to occur and for the
circuit to enter the break before make state.
3. During the T
SD
low period, set the IN
RINGING
and
IN
TEST
inputs to the talk state (0, 0).
4. Release T
SD
, allowing the internal pull-up to
activate the break switches.
When using T
SD
as an input, the two recommended
states are 0 (overrides logic input pins and forces an
all off state) and float (allows switch control via logic
input pins and the thermal shutdown mechanism is
active). This requires the use of an open-collector type
buffer.
Forcing T
SD
to a logic high disables the thermal
shutdown circuit and is therefore not recommended as
this could lead to device damage or destruction in the
presence of excessive tip or ring potentials.
2.2.6 Break-Before-Make Operation for all Version (Ringing to Talk Transition)
2.3 Data Latch
The CPC7582 has an integrated data latch. The latch
operation is controlled by logic-level input pin 11
(LATCH). The data input of the latch is pin 10
(IN
RINGING
) and pin 9 (IN
TEST
) of the device while the
output of the data latch is an internal node used for
state control. When LATCH control pin is at logic 0, the
data latch is transparent and data control signals flow
directly through to state control. A change in input will
be reflected in the switch state. When LATCH control
pin is at logic 1, the data latch is active and a change
in input control will not affect switch state. The
switches will remain in the position they were in when
the LATCH changed from logic 0 to logic 1 and will not
respond to changes in input as long as the latch is at
logic 1. The T
SD
input is not tied to the data latch.
Therefore, T
SD
is not affected by the LATCH input and
the T
SD
input will override state control.
2.4 Thermal Shutdown
Setting T
SD
to +5 V allows switch control using the
logic inputs. This setting, however, also disables the
thermal shutdown circuit and is therefore not
recommended. When using logic controls via the input
pins, pin 7 (T
SD
) should be allowed to float. As a
result, the two recommended states when using pin 7
(T
SD
) as a control are 0, which forces the device to the
all-off state, or float, which allows logic inputs to
remain active. This requires the use of an
open-collector type buffer.
2.5 Ringing Switch Zero-Cross Current Turn Off
After the application of a logic input to turn SW4 off,
the ringing switch is designed to delay the change in
state until the next zero-crossing. Once on, the switch
requires a zero-current cross to turn off, and therefore
should not be used to switch a pure DC signal. The
State
IN
RINGING
IN
TEST
LATCH
T
SD
Timing
Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
Ringing 1 0
0
Floating - Off
On On Off
All-Off 0 0
0
Hold this state for at least one-half of the
ringing cycle. SW4 waiting for zero
current to turn off.
Off Off
On Off
Break-
Before-
Make
0 0 SW4 has opened Off Off Off Off
Talk 0 0 Floating Close Break Switches
On Off Off Off
CPC7582
R05 www.clare.com 15
switch will remain in the on state no matter the logic
input until the next zero crossing. These switching
characteristics will reduce and possibly eliminate
overall system impulse noise normally associated with
ringing switches. See application note AN-144, Impulse
Noise Benefits of Line Card Access Switches. The
attributes of ringing switch SW4 may make it possible
to eliminate the need for a zero-cross switching
scheme. A minimum impedance of 300 Ω in series
with the ringing generator is recommended.
2.6 Power Supplies
Both a +5 V supply and battery voltage are connected
to the CPC7582. CPC7582 switch state control is
powered exclusively by the +5 V supply. As a result,
the CPC7582BC exhibits extremely low power
dissipation during both active and idle states.
The battery voltage is not used for switch control but
rather as a supply for the integrated secondary
protection circuitry. The integrated SCR is designed to
trigger when pin 2 (T
BAT
) or pin 15 (R
BAT
) drops 2 to
4 V below the voltage on pin 16 (V
BAT
). This trigger
prevents a fault induced overvoltage event at the T
BAT
or R
BAT
nodes.
2.7 Battery Voltage Monitor
The CPC7582 also uses the V
BAT
voltage to monitor
battery voltage. If battery voltage is lost, the CPC7582
immediately enters the all-off state. It remains in this
state until the battery voltage is restored. The device
also enters the all-off state if the system battery
voltage goes more positive than –10 V, and remains in
the all-off state until the battery voltage goes more
negative than –15 V. This battery monitor feature
draws a small current from the battery (less than 1 μA
typical) and will add slightly to the device’s overall
power dissipation.
2.8 Protection
2.8.1 Diode Bridge/SCR
The CPC7582 uses a combination of current limited
break switches, a diode bridge/SCR clamping circuit,
and a thermal shutdown mechanism to protect the
SLIC device or other associated circuitry from damage
during line transient events such as lightning. During a
positive transient condition, the fault current is
conducted through the diode bridge to ground via
F
GND
. Voltage is clamped to a diode drop above
ground. During a negative transient of 2 to 4 V more
negative than the voltage at V
BAT
, the SCR conducts
and faults are shunted to F
GND
via the SCR or the
diode bridge.
In order for the SCR to crowbar or foldback, the on
voltage (see “Protection Circuitry Electrical
Specifications” on page 10) of the SCR must be less
negative than the V
BAT
voltage. If the V
BAT
voltage is
less negative than the SCR on voltage or if the V
BAT
supply is unable to source the trigger current, the SCR
will not crowbar.
For power induction or power-cross fault conditions,
the positive cycle of the transient is clamped to the
diode drop above ground and the fault current directed
to ground. The negative cycle of the transient will
cause the SCR to conduct when the voltage exceeds
the V
BAT
voltage by two to four volts, steering the
current to ground.
2.8.2 Current Limiting function
If a lightning strike transient occurs when the device is
in the talk state, the current is passed along the line to
the integrated protection circuitry and limited by the
dynamic current limit response of the active switches
during the talk state. During the talk state, when a
1000V 10x1000 μs pulse (GR-1089-CORE lightning)
is applied to the line though a properly clamped
external protector, the current seen at pins 2 (T
BAT
)
and pin 15 (R
BAT
) will be a pulse with a typical
magnitude of 2.5 A and a duration of less than 0.5 μs.
If a power-cross fault occurs with the device in the talk
state, the current is passed though break switches
SW1 and SW2 on to the integrated protection circuit
and is limited by the dynamic DC current limit
response of the two break switches. The DC current
limit, specified over temperature, is between 80 mA
and 425 mA, and the circuitry has a negative
temperature coefficient. As a result, if the device is
subjected to extended heating due to a power cross
fault, the limited current measured at pin 3 (T
LINE
) and
pin 14 (R
LINE
) will decrease as the device temperature
increases. If the device temperature rises sufficiently,
the temperature shutdown mechanism will activate
and the device will enter the all-off state.
2.9 Temperature Shutdown
The thermal shutdown mechanism will activate when
the device temperature reaches a minimum of 110° C,
placing the device in the all-off state regardless of
logic input. During thermal shutdown mode, pin 7
(T
SD
) will read 0 V. Normal output of T
SD
is +V
DD
.
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CPC7582MCTR

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