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74AVC2T45DP-Q100H

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
74AVC2T45_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 15 February 2013 9 of 23
NXP Semiconductors
74AVC2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
11. Dynamic characteristics
[1] t
pd
is the same as t
PLH
and t
PHL
; t
dis
is the same as t
PLZ
and t
PHZ
; t
en
is the same as t
PZL
and t
PZH
.
t
en
is a calculated value using the formula shown in Section 13.4 “Enable times”
[1] t
pd
is the same as t
PLH
and t
PHL
; t
dis
is the same as t
PLZ
and t
PHZ
; t
en
is the same as t
PZL
and t
PZH
.
t
en
is a calculated value using the formula shown in Section 13.4 “Enable times”
[1] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of the outputs.
[2] f
i
= 10 MHz; V
I
=GNDtoV
CC
; t
r
= t
f
= 1 ns; C
L
= 0 pF; R
L
= .
Table 9. Typical dynamic characteristics at V
CC(A)
= 0.8 V and T
amb
= 25 C
[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6
Symbol Parameter Conditions V
CC(B)
Unit
0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V
t
pd
propagation delay A to B 15.5 8.1 7.6 7.7 8.4 9.2 ns
B to A 15.5 12.7 12.3 12.2 12.0 11.8 ns
t
dis
disable time DIR to A 12.2 12.2 12.2 12.2 12.2 12.2 ns
DIR to B 11.7 7.9 7.6 8.2 8.7 10.2 ns
t
en
enable time DIR to A 27.2 20.6 19.9 20.4 20.7 22.0 ns
DIR to B 27.7 20.3 19.8 19.9 20.6 21.4 ns
Table 10. Typical dynamic characteristics at V
CC(B)
= 0.8 V and T
amb
= 25 C
[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6
Symbol Parameter Conditions V
CC(A)
Unit
0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V
t
pd
propagation delay A to B 15.5 12.7 12.3 12.2 12.0 11.8 ns
B to A 15.5 8.1 7.6 7.7 8.4 9.2 ns
t
dis
disable time DIR to A 12.2 4.9 3.8 3.7 2.8 3.4 ns
DIR to B 11.7 9.2 9.0 8.8 8.7 8.6 ns
t
en
enable time DIR to A 27.2 17.3 16.6 16.5 17.1 17.8 ns
DIR to B 27.7 17.6 16.1 15.9 14.8 15.2 ns
Table 11. Typical power dissipation capacitance at V
CC(A)
= V
CC(B)
and T
amb
= 25 C
[1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions V
CC(A)
and V
CC(B)
Unit
0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V
C
PD
power dissipation
capacitance
A port: (direction A to B);
B port: (direction B to A)
122222pF
A port: (direction B to A);
B port: (direction A to B)
91111121417pF
74AVC2T45_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 15 February 2013 10 of 23
NXP Semiconductors
74AVC2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
[1] t
pd
is the same as t
PLH
and t
PHL
; t
dis
is the same as t
PLZ
and t
PHZ
; t
en
is the same as t
PZL
and t
PZH
.
t
en
is a calculated value using the formula shown in Section 13.4 “Enable times”
Table 12. Dynamic characteristics for temperature range 40 C to +85 C
[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.
Symbol Parameter Conditions V
CC(B)
Unit
1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V
Min Max Min Max Min Max Min Max Min Max
V
CC(A)
= 1.1 V to 1.3 V
t
pd
propagation
delay
A to B 1.0 9.0 0.7 6.8 0.6 6.1 0.5 5.7 0.5 6.1 ns
B to A 1.0 9.0 0.8 8.0 0.7 7.7 0.6 7.2 0.5 7.1 ns
t
dis
disable time DIR to A 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 ns
DIR to B 2.2 8.4 1.8 6.7 2.0 6.9 1.7 6.2 2.4 7.2 ns
t
en
enable time DIR to A - 17.4 - 14.7 - 14.6 - 13.4 - 14.3 ns
DIR to B - 17.8 - 15.6 - 14.9 - 14.5 - 14.9 ns
V
CC(A)
= 1.4 V to 1.6 V
t
pd
propagation
delay
A to B 1.0 8.0 0.7 5.4 0.6 4.6 0.5 3.7 0.5 3.5 ns
B to A 1.0 6.8 0.8 5.4 0.7 5.1 0.6 4.7 0.5 4.5 ns
t
dis
disable time DIR to A 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 ns
DIR to B 2.0 7.6 1.8 5.9 1.6 6.0 1.2 4.8 1.7 5.5 ns
t
en
enable time DIR to A - 14.4 - 11.3 - 11.1 - 9.5 - 10.0 ns
DIRtoB -14.3-11.7-10.9-10.0- 9.8ns
V
CC(A)
= 1.65 V to 1.95 V
t
pd
propagation
delay
A to B 1.0 7.7 0.6 5.1 0.5 4.3 0.5 3.4 0.5 3.1 ns
B to A 1.0 6.1 0.7 4.6 0.5 4.4 0.5 3.9 0.5 3.7 ns
t
dis
disable time DIR to A 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 ns
DIR to B 1.8 7.7 1.8 5.7 1.4 5.8 1.0 4.5 1.5 5.2 ns
t
en
enable time DIR to A - 13.8 - 10.3 - 10.2 - 8.4 - 8.9 ns
DIR to B - 13.2 - 10.6 - 9.8 - 8.9 - 8.6 ns
V
CC(A)
= 2.3V to 2.7V
t
pd
propagation
delay
A to B 1.0 7.2 0.5 4.7 0.5 3.9 0.5 3.0 0.5 2.6 ns
B to A 1.0 5.7 0.6 3.8 0.5 3.4 0.5 3.0 0.5 2.8 ns
t
dis
disable time DIR to A 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 ns
DIR to B 1.7 7.3 2.0 5.2 1.5 5.1 0.6 4.2 1.1 4.8 ns
t
en
enable time DIR to A - 13.0 - 9.0 - 8.5 - 7.2 - 7.6 ns
DIR to B - 11.4 - 8.9 - 8.1 - 7.2 - 6.8 ns
V
CC(A)
= 3.0V to 3.6V
t
pd
propagation
delay
A to B 1.0 7.1 0.5 4.5 0.5 3.7 0.5 2.8 0.5 2.4 ns
B to A 1.0 6.1 0.6 3.6 0.5 3.1 0.5 2.6 0.5 2.4 ns
t
dis
disable time DIR to A 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns
DIR to B 1.7 7.2 0.7 5.5 0.6 5.5 0.7 4.1 1.7 4.7 ns
t
en
enable time DIR to A - 13.3 - 9.1 - 8.6 - 6.7 - 7.1 ns
DIR to B - 11.8 - 9.2 - 8.4 - 7.5 - 7.1 ns
74AVC2T45_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 15 February 2013 11 of 23
NXP Semiconductors
74AVC2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
[1] t
pd
is the same as t
PLH
and t
PHL
; t
dis
is the same as t
PLZ
and t
PHZ
; t
en
is the same as t
PZL
and t
PZH
.
t
en
is a calculated value using the formula shown in Section 13.4 “Enable times”
Table 13. Dynamic characteristics for temperature range 40 C to +125 C
[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6
Symbol Parameter Conditions V
CC(B)
Unit
1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V
Min Max Min Max Min Max Min Max Min Max
V
CC(A)
= 1.1 V to 1.3 V
t
pd
propagation
delay
A to B 1.0 9.9 0.7 7.5 0.6 6.8 0.5 6.3 0.5 6.8 ns
B to A 1.0 9.9 0.8 8.8 0.7 8.5 0.6 8.0 0.5 7.9 ns
t
dis
disable time DIR to A 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 ns
DIR to B 2.2 9.2 1.8 7.4 2.0 7.6 1.7 6.9 2.4 8.0 ns
t
en
enable time DIR to A - 19.1 - 16.2 - 16.1 - 14.9 - 15.9 ns
DIR to B - 19.6 - 17.2 - 16.5 - 16.0 - 16.5 ns
V
CC(A)
= 1.4 V to 1.6 V
t
pd
propagation
delay
A to B 1.0 8.8 0.7 6.0 0.6 5.1 0.5 4.1 0.5 3.9 ns
B to A 1.0 7.5 0.8 6.0 0.7 5.7 0.6 5.2 0.5 5.0 ns
t
dis
disable time DIR to A 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 ns
DIR to B 2.0 8.3 1.8 6.5 1.6 6.6 1.2 5.3 1.7 6.1 ns
t
en
enable time DIR to A - 15.8 - 12.5 - 12.3 - 10.5 - 11.1 ns
DIR to B - 15.8 - 13.0 - 12.1 - 11.1 - 10.9 ns
V
CC(A)
= 1.65 V to 1.95 V
t
pd
propagation
delay
A to B 1.0 8.5 0.6 5.7 0.5 4.8 0.5 3.8 0.5 3.5 ns
B to A 1.0 6.8 0.7 5.1 0.5 4.9 0.5 4.3 0.5 4.1 ns
t
dis
disable time DIR to A 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 ns
DIR to B 1.8 8.5 1.8 6.3 1.4 6.4 1.0 5.0 1.5 5.8 ns
t
en
enable time DIR to A - 15.3 - 11.4 - 11.3 - 9.3 - 9.9 ns
DIR to B - 14.6 - 11.8 - 10.9 - 9.9 - 9.6 ns
V
CC(A)
= 2.3V to 2.7V
t
pd
propagation
delay
A to B 1.0 8.0 0.5 5.2 0.5 4.3 0.5 3.3 0.5 2.9 ns
B to A 1.0 6.3 0.6 4.2 0.5 3.8 0.5 3.3 0.5 3.1 ns
t
dis
disable time DIR to A 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns
DIR to B 1.7 8.0 2.0 5.8 1.5 5.7 0.6 4.7 1.1 5.3 ns
t
en
enable time DIR to A - 14.3 - 10.0 - 9.5 - 8.0 - 8.4 ns
DIR to B - 12.7 - 9.9 - 9.0 - 8.0 - 7.6 ns
V
CC(A)
= 3.0V to 3.6V
t
pd
propagation
delay
A to B 1.0 7.9 0.5 5.0 0.5 4.1 0.5 3.1 0.5 2.7 ns
B to A 1.0 6.8 0.6 4.0 0.5 3.5 0.5 2.9 0.5 2.7 ns
t
dis
disable time DIR to A 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 ns
DIR to B 1.7 7.9 0.7 6.1 0.6 6.1 0.7 4.6 1.7 5.2 ns
t
en
enable time DIR to A - 14.7 - 10.1 - 9.6 - 7.5 - 7.9 ns
DIR to B - 13.1 - 10.2 - 9.3 - 8.3 - 7.9 ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

74AVC2T45DP-Q100H

Mfr. #:
Buy 74AVC2T45DP-Q100H
Manufacturer:
Nexperia
Description:
Translation - Voltage Levels 74AVC2T45DP-Q100/TSSOP8/REEL 7
Lifecycle:
New from this manufacturer.
Delivery:
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