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74AVC2T45DP-Q100H

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74AVC2T45_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 15 February 2013 12 of 23
NXP Semiconductors
74AVC2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
12. Waveforms
[1] V
CCI
is the supply voltage associated with the data input port.
[2] V
CCO
is the supply voltage associated with the output port.
Measurement points are given in Table 14
.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 5. The data input (nA, nB) to output (nB, nA) propagation delay times
001aak114
nA, nB input
nB, nA output
t
PLH
t
PHL
GND
V
I
V
OH
V
M
V
M
V
OL
Measurement points are given in Table 14.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 6. Enable and disable times
001aae968
t
PZL
t
PZH
t
PHZ
t
PLZ
GND
GND
V
I
V
CCO
V
OL
V
OH
V
M
V
M
V
M
V
X
V
Y
outputs
disabled
outputs
enabled
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
DIR input
Table 14. Measurement points
Supply voltage Input
[1]
Output
[2]
V
CC(A)
, V
CC(B)
V
M
V
M
V
X
V
Y
1.1 V to 1.6 V 0.5V
CCI
0.5V
CCO
V
OL
+0.1V V
OH
0.1 V
1.65 V to 2.7 V 0.5V
CCI
0.5V
CCO
V
OL
+0.15V V
OH
0.15 V
3.0 V to 3.6 V 0.5V
CCI
0.5V
CCO
V
OL
+0.3V V
OH
0.3 V
74AVC2T45_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 15 February 2013 13 of 23
NXP Semiconductors
74AVC2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
[1] V
CCI
is the supply voltage associated with the data input port.
[2] dV/dt 1.0 V/ns
[3] V
CCO
is the supply voltage associated with the output port.
Test data is given in Table 15
.
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance.
V
EXT
= External voltage for measuring switching times.
Fig 7. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
C
L
R
T
R
L
R
L
G
Table 15. Test data
Supply voltage Input Load V
EXT
V
CC(A)
, V
CC(B)
V
I
[1]
t/V
[2]
C
L
R
L
t
PLH
, t
PHL
t
PZH
, t
PHZ
t
PZL
, t
PLZ
[3]
1.1 V to 1.6 V V
CCI
1.0ns/V 15pF 2k open GND 2V
CCO
1.65 V to 2.7 V V
CCI
1.0ns/V 15pF 2k open GND 2V
CCO
3.0 V to 3.6 V V
CCI
1.0ns/V 15pF 2k open GND 2V
CCO
74AVC2T45_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 15 February 2013 14 of 23
NXP Semiconductors
74AVC2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
13. Application information
13.1 Unidirectional logic level-shifting application
The circuit given in Figure 8 is an example of the 74AVC2T45-Q100 being used in a
unidirectional logic level-shifting application.
Fig 8. Unidirectional logic level-shifting application
Table 16. Unidirectional logic level-shifting application
Pin Name Function Description
1V
CC(A)
V
CC1
supply voltage of system-1 (0.8 V to 3.6 V)
2 1A OUT1 output level depends on V
CC1
voltage
3 2A OUT2 output level depends on V
CC1
voltage
4 GND GND device GND
5 DIR DIR the GND (LOW level) determines B port to A port direction
6 2B IN2 input threshold value depends on V
CC2
voltage
7 1B IN1 input threshold value depends on V
CC2
voltage
8V
CC(B)
V
CC2
supply voltage of system-2 (0.8 V to 3.6 V)
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74AVC2T45DP-Q100H

Mfr. #:
Buy 74AVC2T45DP-Q100H
Manufacturer:
Nexperia
Description:
Translation - Voltage Levels 74AVC2T45DP-Q100/TSSOP8/REEL 7
Lifecycle:
New from this manufacturer.
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