74AVC2T45_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 15 February 2013 3 of 23
NXP Semiconductors
74AVC2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
5. Functional diagram
6. Pinning information
6.1 Pinning
Fig 1. Logic symbol Fig 2. Logic diagram
001aag577
DIR
1B
2B
7
6
1A
2A
5
2
3
V
CC(A)
V
CC(B)
001aag578
DIR
1B
2B
1A
2A
V
CC(A)
V
CC(B)
Fig 3. Pin configuration SOT505-2 and SOT765-1 Fig 4. Pin configuration SOT996-2
74AVC2T45-Q100
V
CC(A)
V
CC(B)
1A 1B
2A 2B
GND DIR
aaa-006158
1
2
3
4
6
5
8
7
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$
$
9
%
%
74AVC2T45_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 15 February 2013 4 of 23
NXP Semiconductors
74AVC2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] The input circuit of the data I/O is always active.
[3] The DIR input circuit is referenced to V
CC(A)
.
[4] If at least one of V
CC(A)
or V
CC(B)
is at GND level, the device goes into Suspend mode.
Table 3. Pin description
Symbol Pin Description
V
CC(A)
1 supply voltage A (referenced to pins 1A, 2A and DIR)
1A 2 data input or output
2A 3 data input or output
GND 4 ground (0 V)
DIR 5 direction control
2B 6 data input or output
1B 7 data input or output
V
CC(B)
8 supply voltage B (referenced to pins 1B and 2B)
Table 4. Function table
[1]
Supply voltage Input Input/output
[2]
V
CC(A)
, V
CC(B)
DIR
[3]
nA nB
0.8 V to 3.6 V L nA = nB input
0.8 V to 3.6 V H input nB = nA
GND
[4]
XZZ
74AVC2T45_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 15 February 2013 5 of 23
NXP Semiconductors
74AVC2T45-Q100
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
8. Limiting values
[1] The minimum input voltage rating and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] V
CCO
is the supply voltage associated with the output port.
[3] V
CCO
+ 0.5 V should not exceed 4.6 V.
[4] For TSSOP8 package: above 55 C the value of P
tot
derates linearly at 2.5 mW/K.
For VSSOP8 package: above 110 C the value of P
tot
derates linearly with 8 mW/K.
For XSON8 package: above 118 C the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
[1] V
CCO
is the supply voltage associated with the output port.
[2] V
CCI
is the supply voltage associated with the input port.
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC(A)
supply voltage A 0.5 +4.6 V
V
CC(B)
supply voltage B 0.5 +4.6 V
I
IK
input clamping current V
I
<0V 50 - mA
V
I
input voltage
[1]
0.5 +4.6 V
I
OK
output clamping current V
O
<0V 50 - mA
V
O
output voltage Active mode
[1][2][3]
0.5 V
CCO
+0.5 V
Suspend or 3-state mode
[1]
0.5 +4.6 V
I
O
output current V
O
=0VtoV
CCO
- 50 mA
I
CC
supply current I
CC(A)
or I
CC(B)
-100mA
I
GND
ground current 100 - mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation T
amb
= 40 C to +125 C
[4]
-250mW
Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
V
CC(A)
supply voltage A 0.8 3.6 V
V
CC(B)
supply voltage B 0.8 3.6 V
V
I
input voltage 0 3.6 V
V
O
output voltage Active mode
[1]
0V
CCO
V
Suspend or 3-state mode 0 3.6 V
T
amb
ambient temperature 40 +125 C
t/V input transition rise and fall rate V
CCI
= 0.8 V to 3.6 V
[2]
-5ns/V

74AVC2T45DP-Q100H

Mfr. #:
Manufacturer:
Nexperia
Description:
Translation - Voltage Levels 74AVC2T45DP-Q100/TSSOP8/REEL 7
Lifecycle:
New from this manufacturer.
Delivery:
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