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ADN4694EBRZ-RL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
3.3 V, 100 Mbps, Half- and Full-Duplex,
High Speed M-LVDS Transceivers
Data Sheet
ADN4690E/ADN4692E/ADN4694E/ADN4695E
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700 ©2012–2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Multipoint LVDS transceivers (low voltage differential
signaling driver and receiver pairs)
Switching rate: 100 Mbps (50 MHz)
Supported bus loads: 30 Ω to 55 Ω
Choice of 2 receiver types
Type 1 (ADN4690E/ADN4692E): hysteresis of 25 mV
Type 2 (ADN4694E/ADN4695E): threshold offset of 100 mV
for open-circuit and bus-idle fail-safe
Conforms to TIA/EIA-899 standard for M-LVDS
Glitch-free power-up/power-down on M-LVDS bus
Controlled transition times on driver output
Common-mode range: −1 V to +3.4 V, allowing
communication with 2 V of ground noise
Driver outputs high-Z when disabled or powered off
Enhanced ESD protection on bus pins
±15 kV HBM (human body model), air discharge
±8 kV HBM (human body model), contact discharge
±10 kV IEC 61000-4-2, air discharge
±8 kV IEC 61000-4-2, contact discharge
Operating temperature range: −40°C to +85°C
Available in 8-lead (ADN4690E/ADN4694E) and 14-lead
(ADN4692E/ADN4695E) SOIC packages
APPLICATIONS
Backplane and cable multipoint data transmission
Multipoint clock distribution
Low power, high speed alternative to shorter RS-485 links
Networking and wireless base station infrastructure
FUNCTIONAL BLOCK DIAGRAMS
ADN4690E/
ADN4694E
V
CC
GND
RO R
D
RE
DE
A
B
DI
10471-001
Figure 1.
ADN4692E/
ADN4695E
V
CC
GND
RO
R
D
RE
DE
DI
10471-102
A
B
Z
Y
Figure 2.
GENERAL DESCRIPTION
The ADN4690E/ADN4692E/ADN4694E/ADN4695E are
multipoint, low voltage differential signaling (M-LVDS)
transceivers (driver and receiver pairs) that can operate at up
to 100 Mbps (50 MHz). Slew rate control is implemented on the
driver outputs. The receivers detect the bus state with a differential
input of as little as 50 mV over a common-mode voltage range of
−1 V to +3.4 V. ESD protection of up to ±15 kV is implemented
on the bus pins. The parts adhere to the TIA/EIA-899 standard for
M-LVDS and complement TIA/EIA-644 LVDS devices with
additional multipoint capabilities.
The ADN4690E/ADN4692E are Type 1 receivers with 25 mV of
hysteresis, so that slow-changing signals or loss of input does
not lead to output oscillations. The ADN4694E/ADN4695E are
Type 2 receivers exhibiting an offset threshold, guaranteeing the
output state when the bus is idle (bus-idle fail-safe) or the
inputs are open (open-circuit fail-safe).
The parts are available as half-duplex in an 8-lead SOIC package
(the ADN4690E/ADN4694E) or as full-duplex in a 14-lead
SOIC package (the ADN4692E/ADN4695E). A selection table
for the ADN469xE parts is shown in Table 1.
Table 1. High Speed M-LVDS Transceiver Selection Table
Part No.
Receiver
Data Rate
Duplex
ADN4690E
Type 1
100 Mbps
Half
ADN4691E
Type 1
200 Mbps
Half
ADN4692E Type 1 100 Mbps 14-lead Full
ADN4693E Type 1 200 Mbps 14-lead Full
ADN4694E Type 2 100 Mbps 8-lead Half
ADN4695E Type 2 100 Mbps 14-lead Full
ADN4696E Type 2 200 Mbps 8-lead Half
ADN4697E Type 2 200 Mbps 14-lead Full
ADN4690E/ADN4692E/ADN4694E/ADN4695E Data Sheet
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Receiver Input Threshold Test Voltages .................................... 4
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Test Circuits and Switching Characteristics ................................ 11
Driver Voltage and Current Measurements ............................ 11
Driver Timing Measurements .................................................. 12
Receiver Timing Measurements ............................................... 13
Theory of Operation ...................................................................... 14
Half-Duplex/Full-Duplex Operation ....................................... 14
Three-State Bus Connection ..................................................... 14
Truth Tables................................................................................. 14
Glitch-Free Power-Up/Power-Down ....................................... 15
Fault Conditions ......................................................................... 15
Receiver Input Thresholds/Fail-Safe ........................................ 15
Applications Information .............................................................. 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
1/16—Rev. A to Rev. B
Changed NC to DNC .................................................... Throughout
Changes to Table 1 Title ................................................................... 1
Changes to Table 6 ............................................................................ 6
3/12—Rev. 0 to Rev. A
Added ADN4694E and
ADN4695E ................................. Universal
Change to Features Section, General Description Section,
and Table 1 ......................................................................................... 1
Added Type 2 Receiver Parameters, Table 2 ................................. 3
Added Table 4, Renumbered Sequentially ..................................... 5
Added Type 2 Receiver Parameters, Table 5 .................................. 5
Changes to Table 8 ............................................................................. 7
Added Table 13 ............................................................................... 14
Changes to Receiver Input Thresholds/Fail-Safe Section
and Figure 35 ................................................................................... 15
Changes to Figure 36 and Figure 37 and Their Captions ......... 16
Changes to Ordering Guide .......................................................... 18
1/12—Revision 0: Initial Version
Data Sheet ADN4690E/ADN4692E/ADN4694E/ADN4695E
Rev. B | Page 3 of 20
SPECIFICATIONS
V
CC
= 3.0 V to 3.6 V; R
L
= 50 Ω; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Outputs
Differential Output Voltage Magnitude |V
OD
| 480 650 mV See Figure 18
∆|V
OD
| for Complementary Output States ∆|V
OD
| −50 +50 mV See Figure 18
Common-Mode Output Voltage (Steady State) V
OC(SS)
0.8 1.2 V See Figure 19, Figure 22
ΔV
OC(SS)
for Complementary Output States ΔV
OC(SS)
−50 +50 mV See Figure 19, Figure 22
Peak-to-Peak V
OC
V
OC(PP)
150 mV See Figure 19, Figure 22
Maximum Steady-State Open-Circuit Output
Voltage
V
A(O)
, V
B(O)
,
V
Y(O)
, or V
Z(O)
0 2.4 V See Figure 20
Voltage Overshoot
Low to High V
PH
1.2V
SS
V See Figure 23, Figure 26
High to Low V
PL
−0.2V
SS
V See Figure 23, Figure 26
Output Current
Short Circuit |I
OS
| 24 mA See Figure 21
High Impedance State, Driver Only I
OZ
−15 +10 µA –1.4 V ≤ (V
Y
or V
Z
) ≤ 3.8 V,
other output = 1.2 V
Power Off I
O(OFF)
−10 +10 µA –1.4 V ≤ (V
Y
or V
Z
) ≤ 3.8 V,
other output = 1.2 V, 0 V ≤ V
CC
≤ 1.5 V
Output Capacitance C
Y
or C
Z
3 pF V
I
= 0.4 sin(30e
6
πt) V + 0.5 V,
2
other output = 1.2 V, DE = 0 V
Differential Output Capacitance C
YZ
2.5 pF V
AB
= 0.4 sin(30e
6
πt) V,
2
DE = 0 V
Output Capacitance Balance (C
Y
/C
Z
) C
Y/Z
0.99 1.01
Logic Inputs (DI, DE)
Input High Voltage
V
IH
2
V
CC
V
Input Low Voltage V
IL
GND 0.8 V
Input High Current I
IH
0 10 µA V
IH
= 2 V to V
CC
Input Low Current I
IL
0 10 µA V
IL
= GND to 0.8 V
RECEIVER
Differential Inputs
Differential Input Threshold Voltage
Type 1 Receiver (ADN4690E, ADN4692E) V
TH
−50 +50 mV See Table 3, Figure 35
Type 2 Receiver (ADN4694E, ADN4695E) V
TH
50 150 mV See Table 4, Figure 35
Input Hysteresis
Type 1 Receiver (ADN4690E, ADN4692E) V
HYS
25 mV
Type 2 Receiver (ADN4694E, ADN4695E) V
HYS
0 mV
Differential Input Voltage Magnitude |V
ID
| 0.05 V
CC
V
Input Capacitance C
A
or C
B
3 pF V
I
= 0.4 sin(30e
6
πt) V + 0.5 V,
2
other input = 1.2 V
Differential Input Capacitance C
AB
2.5 pF V
AB
= 0.4 sin(30e
6
πt) V
2
Input Capacitance Balance (C
A
/C
B
) C
A/B
0.99 1.01
Logic Output RO
Output High Voltage V
OH
2.4 V I
OH
= –8 mA
Output Low Voltage V
OL
0.4 V I
OL
= 8 mA
High Impedance Output Current I
OZ
−10 +15 µA V
O
= 0 V or 3.6 V
Logic Input RE
Input High Voltage V
IH
2 V
CC
V
Input Low Voltage V
IL
GND 0.8 V
Input High Current
I
IH
−10
0
µA
V
IH
= 2 V to V
CC
Input Low Current I
IL
−10 0 µA V
IL
= GND to 0.8 V
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

ADN4694EBRZ-RL7

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Manufacturer:
Analog Devices Inc.
Description:
LVDS Interface IC MLVDS Xcvr,HD,100M Type 2 Rx,EnhancedESD
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